For Acetronics (again!)

[Adrian]

Hi Alain

I thought you might be interested to see the finished result! I used your basic PCB design layout but generated a slightly different version on CAD. Many thanks for layout, scheme and HEX (I haven't got the French out yet but I'm on the disassembly case!)

Many thanks for your help

Adrian

[Acetronics2]

Nice !!!

Now, the hard work ...

FIND a reliable timebase for Adj cap trimming !!! ...

Regards

Alain

[Adrian]

I agree Alain, however I have come across an article written a number of years ago by a UK amateur G4NJU who describes a pretty good but fairly simple solution. He uses the 15,625Hz TV line frequency which appears to be locked to a Standard. You may have seen the article. If not, he picks up a signal from a Scart socket on a TV or recorder and strips the line sync, also masking the half line pulses during frame blanking (we're talking PAL here!). A simple divide by two to present 7,812.5 Hz to one side of a XOR phase detector. The other side starts with a 10MHz xtal osc. also divided down by 10 and 10 to get standards of 10Mhz, 1 Mhz and 100Khz. Further division of 128 produces 7,812.5 Hz.
The phase comparator feeds a varactor across the xtal to keep the whole lot locked and a centre zero meter shows lock. It apparently compares with Droitwich at 1 part in 10 to the 9. Just 6 chips and a handful of components. I'll try it out in a few days

Kind regards

Adrian