3 phase sequencing


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  1. #1
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    Default 3 phase sequencing

    Hi, here is the requirement;

    I need to monitor the 3 mains phases and detect if (a) one goes dead and (b) if the 3 phases are incorrectly sequenced. The 3 phases are being fed to 3 different pins on a 16F676.

    The first part seems relatively easy; the second one I'm struggling to find a solutioion for. Am I on the right track here?

    The following is for 50 hz;

    I plotted the 3 phase waveforms in Excel, to better visualize the timings, and here is what I feel.

    If the sequence is correct, the time between 2 corresponding points on adjacent phases would be 10.33 ms; this would be twice that if the wires are incorrectly sequenced.

    Now, what makes things complex is that I'd also like to serially be outputtng the 3 readings in a cycle. How can this be done best?

    I suspect the easiest solution lies in Darrel's 'Instant Interrupts' article, but I still dont quite get how the logic should be.

    Has anyone on the list done something similar?

    Thanks for any insight on this.

    Regards,

    Anand
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    Quote Originally Posted by ardhuru View Post
    If the sequence is correct, the time between 2 corresponding points on adjacent phases would be 10.33 ms; this would be twice that if the wires are incorrectly sequenced.
    Sorry, that should have read 6.67 ms.

    Regards,

    Anand

  3. #3
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    Quote Originally Posted by ardhuru View Post
    I need to monitor the 3 mains phases and detect if (a) one goes dead and (b) if the 3 phases are incorrectly sequenced. The 3 phases are being fed to 3 different pins on a 16F676.
    Off the top of my head...just an idea...may or may not work...

    Rectify and regulate each phase, use a zener diode on each phase to get each phase to output a 5v pulse.

    Input each phase's output pulse to RA0-1-2, use the 'Interrupt on Change' feature.

    Set up TMR1 with your oscillator speed (prescalers, etc) so you can get decent resolution and yet be able to count up to 10.33ms.

    Enable RA0/RA1/RA2 I/O/C. Wait for the leading edge of the RA0 pulse using the Interrupt. Save TMR1 value. Wait for the RA1 pulse, save that time. Wait for the RA2 pulse and while waiting, subtract the TMR1 values for the RA1 and RA0 pulses and make sure they're within spec.

    If, for instance, after you get the RA0 pulse, you get the RA2 pulse next, you know you've skipped the RA1 pulse and that phase is probably missing.

    I'm thinking of a sort of 'software latch', where one pulse enables getting another pulse, which in turn enables getting another pulse. If anything other than the pulse you are waiting for shows up, then flag an error. And in the meanwhile waiting for pulses, you do a bit of math to make sure the pulses are coming at the right times.

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    Using Interrupt On Change you'll get an interrupt every 3.33mS. I think all you need to do is check the pin number and polarity of the interrupt (rising/falling) for the sequence and reset a timer set to overflow at ~3.5mS. If the timer overflows, you're missing a phase.

    Of course, you already know you can connect the phases through current limiting resistors as shown in Microchip's AN236.

    If you output A, B, or C for a rising edges and a, b or c for falling edges you should see ABCabcABCabc...
    Last edited by dhouston; - 25th May 2007 at 12:40.

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    I think RA does not have Interrupts.

    Anyway the idea is correct. Another add-on would be to have a learn stage, so the connections of the R-S-T can be memorized first, and then turn into running mode for continuous checking of the sequence.

    Ioannis

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    Hi Skimask, Dave,

    Thanks. Do I understand that both of you are essentially suggesting a similar thing?

    Dave, as you pointed out I have directly input the phases thru' resistors. This effectively gives me only 3 half cycles per 3-phase cycle. For what you suggest would I need to have full-wave rectified signals (6 half cycles) at the inputs?

    Sorry I'm being dense about this but its a first as far as 3 phase design is concerned.

    Regards,

    Anand

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    Sorry I'm being dense about this but its a first as far as 3 phase design is concerned.
    I hope someone's a licensed electrician here - I'm all for the competent hobbyist playing around with single phase (110 -240), but 3 phase 415V being feed to a digital circuit, when I hear someone say "this a first for me", makes me wonder if it's really such a good idea.

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    Point taken!

    I do have lots of experience with transformerless designs, interfacing mains directly with the PIC (as in X10 receivers and transmitters etc.), traic controllers and so on but like I said its the first with 3 phase. So, its more an issue pertaining to the timings involved, rather than electrical aspects.

    Regards,

    Anand

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    Post Loss of AC Voltage Considerations

    Hi Anand,

    [PDF] Loss of AC Voltage Considerations -
    http://www.pes-psrc.org/Reports/Loss...Protection.pdf

    Pasted:
    1.0 Introduction
    Protection of power system elements such as transmission lines, generators, etc., often requires accurate measurement of three-phase voltage to provide reliable fault detection and breaker operations to minimize power system disruptions.
    -Adam-
    Ohm it's not just a good idea... it's the LAW !

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    Quote Originally Posted by ardhuru View Post
    Dave, as you pointed out I have directly input the phases thru' resistors. This effectively gives me only 3 half cycles per 3-phase cycle. For what you suggest would I need to have full-wave rectified signals (6 half cycles) at the inputs?
    Anand, assuming you use pins capable of Interrupt on Change, you'll get an interrupt on both the rising and falling edge. It's the same as using it for ZC detection in AN236 which also discusses the slight assymetry because of different trigger voltages for rising vs. falling edges.

    Look at the second oscilloscope screenshot on this page. It's a ZC detector on pin 13 of the PIC.The protection diodes on the pin effectively give you a square wave. In your case, the higher voltage will give steeper edges. You'll get 100 interrupts per second per phase or 300 total per second.

    Interrupt on Change cannot be preset for falling or rising edges. It interrupts on both and sets register bits to indicate the pin and rising or falling. On each interrupt you reset the timer, check the register bits to determine pin & polarity, clear the interrupt and output your coded representation of the event.

    P.S. What I'm suggesting is much, much simpler than what Skimask suggested.
    Last edited by dhouston; - 25th May 2007 at 17:24.

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    Quote Originally Posted by dhouston View Post
    Anand, you'll get an interrupt on both the rising and falling edge.

    In your case, the higher voltage will give steeper edges. You'll get 100 interrupts per second per phase or 300 total per second.

    Interrupt on Change cannot be preset for falling or rising edges. It interrupts on both and sets register bits to indicate the pin and rising or falling. On each interrupt you reset the timer, check the register bits to determine pin & polarity, clear the interrupt and output your coded representation of the event.
    Great, Dave! Thats exactly what I needed to be on the right track.

    Thanks again.

    Regards,

    Anand

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    I have done exactly what you describe.

    I used 3 opto-isolators. Each opto had a diode in series and another diode across the LEDs so that they can't possibly get reverse-biased.

    I used a 15K 1W resistor in series for current limiting. It "looks" only at the positive half-cycles. The output of the phototransistor is close to a square wave, and is - of course, totally isolated. It works fine at both 110V and 230V.

    I can give you more details if you are interested in pursuing this approach.
    Charles Linquist

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    Charles, I am *extremely* interested in knowing more about your technique.

    The hardware side is somewhat different from yours, but I too end up with a 'somewhat' square wave (half cycles only) at the pic input. And since I am not interested in the absolute values, I guess that difference can stay.

    I would however love to know more about the software approach you used.

    Thanks and regards,

    Anand

  14. #14
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    This code wasn't interrupt-driven, because it didn't need to be
    By changing "PhaseDelay" you can make it work for either 60 or
    400 hz, or by using PULSIN, you can make it auto-sensing.




    CheckACPhase:
    HighTimer = 0
    CheckPhaseA:
    IF PhaseA = 0 THEN ' Voltage is present or else wouln't be low
    WHILE PHASEA = 0:WEND
    HighTimer = 0
    GOTO CheckPhaseB
    ENDIF
    Pauseus PhaseDelay
    HighTimer = HighTimer + 1
    IF HighTimer => 10 THEN GOTO PhaseAError
    GOTO CheckPhaseA
    PhaseAError: ; No phase A - was never low in 930 uSec period
    StatINfo.0 = 0 ; Can't check for proper phasing, so give error
    HighTimer = 0
    CheckPhaseB:
    If PhaseB = 0 THEN
    StatInfo.3 = 0 'Erase the error
    HighTimer = 0
    Goto CheckPhaseC
    ENDIF
    WaitForLowB:
    Pauseus PhaseDelay
    IF PhaseB = 0 THEN goto PhaseBError2
    HighTimer = HighTimer + 1
    IF HighTimer => 10 THEN GOTO PhaseBError1
    GOTO WaitForLowB
    PhaseBError1: ; No signal
    StatINfo.1 = 0 ; Can't check for proper phasing, so give error
    HighTimer = 0
    GOTO CheckPhaseC
    PhaseBError2: ; Signal, but wrong phase

    HighTimer = 0
    CheckPhaseC:
    If PhaseC = 0 THEN
    Goto DunPhaseCheck
    ENDIF
    Pauseus PhaseDelay
    HighTimer = HighTimer + 1
    IF HighTimer => 10 THEN GOTO PhaseCError
    GOTO CheckPhaseC
    PhaseCError:
    StatInfo.2 = 0

    DunPhaseCheck:
    IF Statinfo.0 = 0 or StatInfo.1 = 0 OR Statinfo.2 = 0 Then
    StatInfo.3 = 1
    ENDIF
    RETURN



    ; When returned, Statinfo bit 3 = 0 = OUT OF PHASE
    ; bit 0 = 0 = PhaseA not present
    ; bit 1 = 0 = PhaseB not present
    ; bit 2 = 0 = PhaseC not present
    ; When any phase is not present, bit 3 is always SET.
    Charles Linquist

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    Wow, Charles, the whole thing on a platter!

    Thank you so much. Appreciate your sharing the code.

    Regards,

    Anand

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