Hi All,

As HSERIN and HSEROUT are working well on my 18F1220, I can't make DEBUGIN work (DEBUG is okay).

I couldn't find any information searching in the forum and googeling around so if somebody has a clue where I'm missing something...

Code:
@ __CONFIG  _CONFIG1H, _IESO_OFF_1H & _FSCM_OFF_1H & _INTIO1_OSC_1H ; OSC1 as RA7, OSC2 as RA6
@ __CONFIG  _CONFIG2L, _BORV_27_2L & _BOR_OFF_2L & _PWRT_OFF_2L
@ __CONFIG  _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H
@ __CONFIG  _CONFIG3H, _MCLRE_OFF_3H
@ __CONFIG  _CONFIG4L, _DEBUG_OFF_4L & _LVP_ON_4L & _STVR_ON_4L
@ __CONFIG  _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
@ __CONFIG  _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
@ __CONFIG  _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
@ __CONFIG  _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
@ __CONFIG  _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
@ __CONFIG  _CONFIG7H, _EBTRB_OFF_7H

OSCCON  = %01110000 'set INTRC to 8 MHZ
OSCTUNE = %00000000 'OSCILLATOR TUNING REGISTER
ADCON0  = %00000000 'A/D CONTROL REGISTER 0
ADCON1  = %00000000 'A/D CONTROL REGISTER 1
ADCON2  = %00000000 'A/D CONTROL REGISTER 2
INTCON  = %00000000 'INT CTRL REG
INTCON2 = %00000000 'INT CTRL REG 2
INTCON3 = %00000000 'INT CTRL REG 3
PORTA   = %00000000 'State High (1) or Low (0)
TRISA   = %00000000 'Data Direction Control Register (Input/Output)
PORTB   = %00000000 'State High (1) or Low (0) 
TRISB   = %00010000 'Data Direction Control Register (Input/Output)
                            
Define OSC 8            ' Oscillator speed in MHz: 3(3.58) 4 8 10 12 16 20 24 25 32 33 40
DEFINE HSER_CLROERR 1   ' Clear overflow automatically
DEFINE NO_CLRWDT 1      ' Don't waste cycles clearing WDT 

DEFINE DEBUG_REG PORTB 
DEFINE DEBUG_BIT 1 
DEFINE DEBUG_BAUD 9600
DEFINE DEBUG_MODE 0
DEFINE DEBUGIN_REG PORTB
DEFINE DEBUGIN_BIT 4
DEFINE DEBUGIN_MODE 0

SData   VAR BYTE(5)
TimeOut CON 100

MAIN:

    ' Send some serial data with ID as header from Serial Comm Terminal
    DEBUGIN TimeOut,MAIN,[WAIT("ID"),str SData\5] 

    ' Display received data
    DEBUG str SData\5 ,13

    GOTO MAIN

END