divide a 10 Mhz signal by 1000 ...

[F1CHF]

I must divide a signal (10 Mhz) to 10 Khz (OCXO asservissement with a GPS)
I have an example in language "C" and I understand quite nothing !!! it use a 12F675 (clock is the 10 mhz signal)
and I would like to understand why I see all those "counts" for one division

I Hope somebody can help me, I think that I have to write in ASM language, not in Basic
ASM is not easy for me ...
so if somebody knows how to divide a 10 Mhz signal to get a 10 Khz output signal
I would appreciate
thanks
Francois F1CHF
here is the "code" see attached file (sorry I didn't know how to use the "code" function !)

[pedja089]

Just cascade 3 times 4017. It cheapest and reliable way to do it.
https://www.ti.com/lit/ds/schs027c/s...oogle.com%252F

[richard]

I would like to understand why I see all those "counts" for one division

its not one division its three with a 90 deg phase shift on one of them.

one div would be like this

;In simple terms  toggle a pin on every 125th cycle
;start:;set gpio pin high
;delay 124 cycles
;set gpio pin low
;delay 122 cycles
;goto start


CNT VAR BYTE BANK0
TRISIO=110
ASM
START
  BSF GPIO , 0  
  MOVLW 40      ;2
  MOVWF _CNT    ;1
DL1             ;119 DELAY = 2+3(CNT-1)
  DECFSZ _CNT    
  GOTO DL1      
  NOP           ;1
  NOP           ;1
  BCF GPIO , 0  
  MOVLW 40      ;2
  MOVWF _CNT    ;1
DL2
  DECFSZ _CNT    ;119 DELAY = 2+3(CNT-1)
  GOTO DL2      
  GOTO START    ;2
ENDASM

[F1CHF]

thanks Richard I don't see my first reply
so I was saying
"I am not spleeping just trying to undersatnd your asm example ..."
hold the line !
regards

[richard]

i tested my code while i had the sim running, seems i cant count well

this is better

 #CONFIGcfg = _HS_OSC                 ; HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
cfg&= _WDT_ON                 ; WDT enabled
cfg&= _PWRTE_OFF              ; PWRT disabled
cfg&= _MCLRE_ON               ; GP3/MCLR pin function is MCLR
cfg&= _BODEN_ON               ; BOD enabled
cfg&= _CP_OFF                 ; Program Memory code protection is disabled
cfg&= _CPD_OFF                ; Data memory code protection is disabled
  __CONFIG cfg


#ENDCONFIG
 ;pic12f675
;In simple terms  toggle a pin   every 125 cycles
;start:;set gpio pin high
;delay 125 cycles
;set gpio pin low
;delay 123 cycles
;goto start




CNT VAR BYTE BANK0
TRISIO=%11111110
ASM
START
  BSF GPIO , 0  
  MOVLW 41      ;2
  MOVWF _CNT    ;1
DL1             ;122 DELAY = 2+3(CNT-1)
  DECFSZ _CNT,f    
  GOTO DL1
  BCF GPIO , 0  
  MOVLW 40      ;2
  MOVWF _CNT    ;1
DL2
  DECFSZ _CNT,f    ;119 DELAY = 2+3(CNT-1)
  GOTO DL2    
  NOP           ;1  
  GOTO START    ;2
ENDASM

[F1CHF]

I got a very nice answer on that subject
here
Hello François

Have an eye Here: http://www.leapsecond.com/pic/picdiv.htm

Alain

[F1CHF]

thanks for your reply, i know ths solution with divider like 74xx390 etc ... CD4017 at 10 mhz ... not sure ...
objective : have a small unit to do the job !
thanks
francois