DEFINE RESET_ORG and DEC modifier issue

[Marcick]

Sorry I open again a thread but the other one was not exact in the question.

In the code below I use a simple DEC modifier to output a string and it works as expected.
But If I use the "DEFINE RESET_ORG 1EC00h" it doesn't work and the devices seems to reset continuously.
How is it possible ?

' DEFINE RESET_ORG 1EC00h
' device=PIC18F67K22


    #CONFIG
    CONFIG  RETEN = ON          ; Enabled
    CONFIG  INTOSCSEL = LOW      ; LF-INTOSC in High-power mode during Sleep
    CONFIG  SOSCSEL = DIG        ; 
    CONFIG  XINST = OFF           ; Disabled
    CONFIG FOSC = INTIO2        ; Internal RC oscillator
    CONFIG  PLLCFG = OFF           ; Enabled
    CONFIG  FCMEN = OFF           ; Disabled
    CONFIG  IESO = OFF            ; Disabled
    CONFIG  PWRTEN = OFF          ; Disabled
    CONFIG  BOREN = SBORDIS       ; Enabled in hardware, SBOREN disabled
    CONFIG  BORV = 2              ; 2.0V
    CONFIG  BORPWR = ZPBORMV      ; ZPBORMV instead of BORMV is selected
    CONFIG  WDTEN = OFF
    CONFIG  WDTPS = 256           ; 1:256
    CONFIG  RTCOSC = SOSCREF      ; RTCC uses SOSC
    CONFIG  CCP2MX = PORTC        ; RC1
    CONFIG  MSSPMSK = MSK7        ; 7 Bit address masking mode
    CONFIG  MCLRE = ON            ; MCLR Enabled, RG5 Disabled
    CONFIG  STVREN = ON           ; Enabled
    CONFIG  BBSIZ = BB2K          ; 2K word Boot Block size
    CONFIG  DEBUG = OFF           ; Disabled
       CONFIG  CP0 = OFF             ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
    CONFIG  CP1 = OFF             ; Block 1 (004000-007FFFh) code-protected
    CONFIG  CP2 = OFF             ; Block 2 (008000-00BFFFh) code-protected
    CONFIG  CP3 = OFF             ; Block 3 (00C000-00FFFFh) code-protected
    CONFIG  CP4 = OFF             ; Block 4 (010000-013FFFh) code-protected
    CONFIG  CP5 = OFF             ; Block 5 (014000-017FFFh) code-protected
    CONFIG  CP6 = OFF             ; Block 6 (01BFFF-018000h) code-protected
    CONFIG  CP7 = OFF             ; Block 7 (01C000-01FFFFh) code-protected
    CONFIG  CPB = ON             ; Boot Block (000000-0007FFh) code-protected
    CONFIG  CPD = OFF             ; Data EEPROM code-protected
    CONFIG  WRT0 = OFF            ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
    CONFIG  WRT1 = OFF            ; Block 1 (004000-007FFFh) not write-protected
    CONFIG  WRT2 = OFF            ; Block 2 (008000-00BFFFh) not write-protected
    CONFIG  WRT3 = OFF            ; Block 3 (00C000-00FFFFh) not write-protected
    CONFIG  WRT4 = OFF            ; Block 4 (010000-013FFFh) not write-protected
    CONFIG  WRT5 = OFF            ; Block 5 (014000-017FFFh) not write-protected
    CONFIG  WRT6 = OFF            ; Block 6 (01BFFF-018000h) not write-protected
    CONFIG  WRT7 = OFF            ; Block 7 (01C000-01FFFFh) not write-protected
    CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) not write-protected
    CONFIG  WRTB = OFF            ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
    CONFIG  WRTD = OFF            ; Data EEPROM not write-protected
    CONFIG  EBRT0 = OFF           ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT1 = OFF           ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT2 = OFF           ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT3 = OFF           ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT4 = OFF           ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT5 = OFF           ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT6 = OFF           ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRT7 = OFF           ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks
    CONFIG  EBRTB = OFF           ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
    #ENDCONFIG


    DEFINE            OSC            8
    DEFINE            HSER2_RCSTA        90H
    DEFINE          HSER2_TXSTA      24H
    DEFINE             HSER2_BAUD        19200
    DEFINE            HSER2_CLROERR    1


    CLEAR
    OSCCON        =
100000            ; Primary oscillator, internal 8MHz
    OSCCON2.0    =1
    OSCTUNE.7    =1
    Adr            VAR    WORD


loop1:
    FOR Adr=1000 TO 1005
        HSEROUT2 ["test1: ",13,10]                ' -->>>> this works always
        HSEROUT2 ["test2: ", DEC4 Adr,13,10]     ' -->>>> this works only if you comment the first line "DEFINE RESET_ORG 1EC00h"
    NEXT Adr
    PAUSE 1000
    CLEARWDT
    goto loop1

[richard]

the obvious thing is that the bootloader is not right.
is the pbp re-entry point from bootloader correct ?
is the bootloader really capable of 128k operation ? eg are all the two word commands goto ,lfsr ... correctly configured
have the pbp shared lib routines been corrupted or inappropriately shifted ?
have you compared the lst files of working and no working code ?

or are you trying to make a bootloader ?
if so then have you enough room between 1ec00h and the end of memory to fit the
shared pbp routines library ? long version may be a fair bit bigger

[Marcick]

uhhmmm.... where do you see I'm using a bootloader?
Well, I was really working on a bootloader but when I started to see this issue I wrote this simple code (not involving bootloader) to make this post.
I'm talking here also http://support.melabs.com/forum/picb...modifier-issue

[richard]

. where do you see I'm using a bootloader?

my bad, i was thinking back to bootloader issues i had with a 87j11 and 128k relocations going bad
with similar results.

a quick look at a lst file of your code shows a fair bit of this going on for the "DEC" section of your code
the upper portion of the hserout2j label address is ignored.

                          M     endif01EE4E 6A1C               M         clrf    (R2)   + 2
01EE50 6A1D               M         clrf    (R2)   + 3
                      00270         HSEROUT2DEC?    
                          M         MOVE?CW HSEROUT2J, R8     /// hserout2j  is a  more than a word long when >64k
                          M     ifdef USE_LINKER
                          M         CHK?RP  R8
                          M         movlw   low (HSEROUT2J)
                          M         movwf   R8
                          M         movlw   high (HSEROUT2J)
                          M         movwf   (R8)   + 1

hserout2j being a label

HSEROUT2                          0001EC06HSEROUT2?C                        
HSEROUT2COUNT?C                   
HSEROUT2DEC?                      
HSEROUT2J                         0001EC04
HSEROUT2J_USED                    00000001
HSEROUT2NUM?W                     
HSEROUT2_USED                     00000001
HSER_BAUD                         00000960
HSER_BITS                         00000008

[Marcick]

hi,
It's a very long time I don't eat assembly...
Are you saying it's a PBP bug?

[richard]

i'm not really sure what exactly the code is doing but the highlighted sections are doing something with the label but ignoring the upper byte of its address. below 64k its not an issue i would not say its bug , more like its not designed to be relocated beyond the 64k boundary.
anyways its the only thing i see in the code thats likely to be an issue.

01EE52 0E04               M         movlw   low (low (HSEROUT2J))MPASM 5.61                          MCKD.ASM   1-30-2021  23:44:34         PAGE 32




LOC  OBJECT CODE     LINE SOURCE TEXT
  VALUE


01EE54 6E0A               M         movwf   R8
                          M       endif
                          M     endif
                          M         MOVE?CB high (HSEROUT2J), (R8) + 1
                          M         CHK?RP  (R8) + 1
                          M     if ((((R8) + 1) & 8000h) != PREV_ALT)
                          M       if (((R8) + 1) & 8000h)
                          M         bsf     WDTCON, ADSHR
                          M       else
                          M         bcf     WDTCON, ADSHR
                          M       endif
                          M PREV_ALT = ((R8) + 1) & 8000h
                          M     endif
                          M     if (((((R8) + 1) & 0fffh) > BANKA_END) & ((((R8) + 1) & 0fffh) < (0f01h + BANKA_END)))
                          M       if ((((R8) + 1) & 0f00h) != (PREV_BANK << 8))
                          M         movlb   high ((R8) + 1)
                          M PREV_BANK = high ((R8) + 1)
                          M       endif
                          M     endif
                          M     if (low (high (HSEROUT2J)) == 0)
                          M         clrf    (R8) + 1
                          M     else
                          M       if (low (high (HSEROUT2J)) == 255)
                          M         setf    (R8) + 1
                          M       else
01EE56 0EEC               M         movlw   low (high (HSEROUT2J))
01EE58 6E0B               M         movwf   (R8) + 1