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  1. #1
    Join Date
    Dec 2010
    Melbourne Australia

    Default Question Regarding A>D Conversion

    When configuring an A>D conversion, we all know that configuring it to process too quickly can provide erroneous results, but if you go the other way and say configure max A/D Acquisition time select bits (say 20 TAD) and max A/D conversion clock select bits (say Fosc/64). can doing that compromise the aquisition quality in any way (assuming we're in no hurry)?

    It's just reading the datasheet for the PIC18F27J53 it says (p367):
    "For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table 31-30 for more information)."

    Param 130:
    130-------TAD-------A/D Clock Period-----0.8-----12.5(1)-----us-------TOSC based, VREF  3.0V

    Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

    So, I'm assuming the acquisition time can be safely long, but the conversion time?



  2. #2
    Join Date
    May 2013

    Default Re: Question Regarding A>D Conversion

    the simple way to look at it, is that the voltage held in the sample capacitor is slowly bleeding away as the conversion proceeds,
    the quicker you do it the better as long as minimum tad observed. excess acquisition time is not critical
    This is more entertaining than Free to Air TV

  3. #3
    Join Date
    Dec 2010
    Melbourne Australia

    Default Re: Question Regarding A>D Conversion

    Thanks again Richard.



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