Confirm 18f47k40 MSSP setting and allocation using PSS


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  1. #1
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    Default Confirm 18f47k40 MSSP setting and allocation using PSS

    Hi guys

    I am trying to set the MSSP1,2 SPI with the PSS control of the pins and like to confirm i have it correct for the 18f47k40

    first time using MSSP with PPS chip with this arrangement

    also like to confirm SS pin when SSP2 set as slave , when selected as not used is free for other I/O use

    using MPLAB - code configure as guide , it gives warnings on SS is allocated incorrectly , also that SCK2 has no output,( it a slave so there is none ),
    - can SS pin for SPI slave NOT be assigned and is free for other I/O

    i am aware the data pins for both SSP must be allocated even if not used , week pullups assigned to those

    Requirement>

    have MSSP1 as master, generate clock output from clk pin , usedata from buffer byte for SSP1 , no data input pin required , no slave SS output to slave
    Have MSSP2 as slave , recieve clock in , use data from buffer byte for SSP2, no data input pin required , no slave SS pin used / required

    USE: generate 2 seperate spi data streams based off the master generated clock , with slave clock in wire linked to master clock out


    Cheers

    Sheldon


    PPS pin allocation of MSSP1,2 requirement shown here
    Code:
     '  -------   Port B Settings & directions  ----------
        ANSELB  = %00000000          ' Set PortB Analog bit7-0 = ANB7-0 / 0 = digital ,1= Analog ,   
        TRISB   = %10110010          '     
        WPUB    = %00110000          ' Set Week Pullups on Digital inputs POR =0  
        INLVLB  = %11111111          ' Set Input levels - Schmitt = 1 / TTL = 0  POR = 1 
        SLRCONB = %11111111          ' Set Slew Rate 1 = Rate Limited  0 = Max rate POR =1 
        IOCBP   = %00000000          ' IOC Positive Edge Trigger Select RB7-RB0  0 = diabled 1 = enabled POR = 0
        IOCBN   = %00000000          ' IOC Negative Edge Trigger Select RB7-RB0  0 = diabled 1 = enabled POR = 0
        ODCONB  = %00000000          ' Open Drain 0 = Output drives both High and Low signals  1= Output drives Low going signals only POR = 0
           
      ' -------   Setup port B Variables  ----------                       
        LATB   = $00                 '  Clear Outputs
        SSP1_CLKout     VAR LATB.0       '  (active high)
        SSP2CLKIN       VAR PORTB.1      ' wired to portb.0
        SSP1_data        VAR LATB.2       '  SSP1_SDO  DATA OUT  
        SSP2_data       VAR LATB.3       ' ,SSP2_SDO  DATA OUT  
        SSP2_SDI        VAR PORTB.4      ' MSSP2 IN - MUST ASSIGN PIN , BUT NOT CONNECTED 
        SSP1_SDI       VAR PORTB.5      ' MSSP1 IN - MUST ASSIGN PIN , BUT NOT CONNECTED 
      
      ' NOTE: USB-TX2,RX2 - PORTB.6,7 Set by Defines for terminal2 services

    Code:
       RB0PPS =$0F              ' MSSP1(SCK OUTPUT) SCK    SPI MASTER - PORTB.0 USED 
       RB2PPS =$10              ' MSSP1(SDO OUTPUT) SSP1_data     SPI MASTER - PORTB.2 USED  ( PCB REWIRED PORTA.5 TO SUIT ) 
       SSP1CLKPPS=$08           ' MSSP1(SCK INPUT) MSSP1 CLK   SPI MASTER - INPUT MUST BE SET THE SAME PIN AS MSSP1 OUTPUT - PORTB.0 FOR PPS 
       SSP1DATPPS=$0D           ' MSSP1(SDO INPUT) MSSP1 SDI-1 SPI MASTER - INPUT NOT USED BUT MUST BE SET - PIN CANT BE USED FOR OTHER ASSINGMENTS AND IS LEFT NOT CONNECTED - RE-ASIGNED PORTB.5 - RTC_32KHZ 
      'SSP1SSPPS=NA'            ' MSSP1(SS1 INPUT) NOT REQUIRED - DISABLED - NORMAL I/O USE OF PIN              ' 
       
       RB1PPS =$11              ' MSSP2(SCK OUTPUT) MSSP2 CLK  SPI SLAVE  - OUTPUT MUST BE SET THE SAME PIN AS MSSP2 INPUT PORT PORTB.1 FOR PPS  
       RB3PPS =$12              ' MSSP2(SDO OUTPUT) SSP2_data    SPI SLAVE  - PORTB.3 USED  ( PCB REWIRED PORTA.6 TO SUIT ) 
       SSP2CLKPPS=$09           ' MSSP2(SCK INPUT) MSSP2 CLK   SPI SLAVE  - INPUT MUST BE SET THE SAME PIN AS MSSP1 OUTPUT - PORTB.1 FOR PPS 
       SSP2DATPPS=$0C           ' MSSP2(SDO INPUT) MSSP2 SDI-1 SPI SLAVE  - INPUT NOT USED BUT MUST BE SET - PIN CANT BE USED FOR OTHER ASSINGMENTS AND IS LEFT NOT CONNECTED - RE-ASIGNED PORTB.4 - HUB_A 
      'SSP2SSPPS=NA'            ' MSSP2(SS2 INPUT) NOT REQUIRED - DISABLED - NORMAL I/O USE OF PIN              ' 
       
       
    ' -----------MSSP1 & MSSP2 - HARDWARE SPI/I2C SETTINGS ----------------
       
        SSP1STAT = $40   '0100 0000  - bit7 = 0 spi master-sample middle of data output tim, bit6= 1 spi tx occures from active to idel state  
        SSP1CON1 = $2A   '0010 1010  - bit7,6 = x,bit5= spien 1=spi enable - set sck, sdo,sdi ssx pins bit4 = spi ckp 1 =clock idle high 0 = clk idel low,bit3-0- 1010= spi master fosc/4 sspxadd >=1   
        SSP1ADD = 1      ' set master spi address = 1 - cant be 0 
       
        SSP2STAT = $40   '0100 0000  bit7 spi slave mode = bit must be 0 , 
        SSP2CON1 = $25   '0010 0101  bit 7,6= x, bit 5= spien 1=spi enable ,bit4 0 = clk idle low  bit3-0= 0101 spi slave mode SSx pin control disabled
        SSP2CON3 = $0

  2. #2

    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    FWIW there's a really good tool for setting PPS on GCB. Google for PPS Tool for GCB, it really does take the agro out of PPS.
    George

  3. #3

    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    I strongly recommend that you rethink those connections and use the SS input on the slave.

    Without it, if there's ever a single glitch on the SCK (like might happen when you're initializing everything) then the two sides will be out of sync forever with no way to get it working again.

  4. #4
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    hi tumble weed

    with this configuration i cant see how the SS pin on a slave can ensure that it is in sync to CLK from master , even if the master controls the SS pin as the master is not sending data to the slave, and the normal full duplex coms can not be performed

    the SS pin can be turned off in software for slave , but PPS seems to want it to be defined with its config for a slave MSSP , and i thinking i may need to assign it the SSP2- slave input

    The slave SS even if it were turned on would need to be in a "selected State" at all times anyway from what i can see using this config

    SS enable , tied to the master CLK is not going to work and still does not ensure data to CLK is in sync on slave ?


    TOWLERG - ill take a look at the PPS tool

    cheers

    Sheldon

  5. #5
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    in my original drafts of this code [p10 dual colour led panel] i did use cs/ss signals to sync transmission.
    it turned out that the time taken to clear/set cs pin and the impost of two extra pins was as waste of resources an an unnecessary
    complication. it works fine with out it.
    i don't have a k40 chip to test with and don't see why mcc insists on a ss pin . i developed code on a k22 chip
    and did not use the ss2 pin , loss of a pin is not tragic.

    sheldons comments are cluttering the story and some are just incorrect
    this is what i would use

    Code:
    TRISB  = $F2 
    TRISD  = $FF    ;ss2
    ANSELD = $FE  ;ss2
    ANSELB = $C0 ; just the spi pins
    
    
    WPUD   = $01  ;ss2 
    WPUB   = $30 ; just the spi pins
    
    
    
    
    RB0PPS = $0F             ;RB0->MSSP1:SCK1     
    RB2PPS = $10             ;RB2->MSSP1:SDO1     
    RB3PPS = $12             ;RB3->MSSP2:SDO2 
    SSP1CLKPPS = $08         ;RB0->MSSP1:SCK1     
    SSP2DATPPS = $0D         ;RB5->MSSP2:SDI2  
    SSP1DATPPS = $0C         ;RB4->MSSP1:SDI1     
    SSP2CLKPPS = $09         ;RB1->MSSP2:SCK2     
    SSP2SSPPS = $18          ;RD0->MSSP2:SS2    it seems to insist on an ss pin
    
    
    SSP1STAT = $40  ;bog standard spi
    SSP1CON1 = $2A  ;fosc/4 with ssp1add divider
    SSP1ADD  = $01   ; clock divide 2
    SSP2STAT = $40   ;bog standard spi
    SSP2CON1 = $25 ;bog standard spi no ss
    
    ;spi pin allocations
    '    sck1        PORTB.0       
    '    sck2        PORTB.1      ' wired to portb.0
    '    sdo1        PORTB.2      
    '    sdo2        PORTB.3       
    '    sdi2        PORTB.4      
    '    sdi1        PORTB.5      
    '    ss2         PORTD.2
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  6. #6
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    if the PPS sets the unused SS pin on SS2 to portd.0 , can this pin be used for other I/O ?

  7. #7
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    if the PPS sets the unused SS pin on SS2 to portd.0 , can this pin be used for other I/O ?
    thats the question
    the other question is , if you don't set a pin will spi2 still function
    Last edited by richard; - 16th February 2020 at 00:31.
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  8. #8
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    thats the question
    the other question is , if you don't set a pin will spi2 still function

    The answer from the testing is
    1. Not Setting SS pin for ssp2 on the PPS does not appear to effect SSP2 running in this config
    2. assigning SS on the PPS to portd.0 for SSP2 does not appear to effect SSP2 running or effect the I/O operation ( both in and out of Portd.0 ) , which was in use for other items

    Cheers

    Sheldon

  9. #9

    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    it turned out that the time taken to clear/set cs pin and the impost of two extra pins was as waste of resources an an unnecessary
    complication. it works fine with out it
    Yes, it works fine without it until it doesn't.

    The SPI slave counts 8 clocks on SCLK in order to set BF to let you know you have a byte.
    When the slave uses the SS input, that bit counter is reset when SS goes high. That keeps
    you in sync with the master.

    Without it, if there's ever a single glitch on the SCLK line the bit counter will be wrong and you can never resync master -> slave.
    That also means that when you first power up, depending on who gets initialized first, there's a chance that the slave could see a transition on SCLK and you never get sync'd to begin with.

    @Sheldon - I reread your requirements and I have to admit I'm not sure what you're trying to do.
    If I read the comments correct you say that the slave isn't going to use data in. What would be the purpose of the slave?

  10. #10
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    Although usually not necessary, there is a PPS Unlock sequence that is missing in the above code:
    Code:
    PPSLOCK = $55
    PPSLOCK = $AA
    PPSLOCK.0 = 0
    Also, I checked on available Ports for MSSP1/2 Functions and PORTB seems to work for all but SS; which A & D are the only usable PORTS for that. Just noting.

  11. #11
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    @tumbleweed
    although its sheldon's project the code is mine
    If I read the comments correct you say that the slave isn't going to use data in. What would be the purpose of the slave?
    neither spi port reads in any data . the purpose is to send two simultaneous bit streams synced by the same clock.
    p10 led modules rgb or dual colour receive the pixel data per colour in that manner

    it works fine without ss2
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  12. #12

    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    the purpose is to send two simultaneous bit streams synced by the same clock
    I see now what you're doing.

    You're right, no SS needed. Sorry about the noise.

  13. #13
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    You're right, no SS needed. Sorry about the noise.
    its not noise, it was an issue that i initially considered and worth a mention.

    the main issue for me was that mcc insists on a ss pin whether you configure to use it or not on that chip . i have not got a chip to
    experiment with which left me unsure of what was required.
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  14. #14
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    in this config ,if microchip had considered it would have been nice to allow the master and slave not to have a data input pin Have to be assigned , allowing for them to be used as I/O

    the master where no slave is needed still need the data input port assigned in PPS and SSP from the setting i have seen


    test.JPG
    Last edited by longpole001; - 16th February 2020 at 23:10.

  15. #15
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    a spi port without sdi would not be a spi port it would be something else.

    not sure what you mean by ssp . ss=slave select,its an input pin.
    a spi master port has no ss pin there is no such thing as ss out, ss is an optional input signal for spi slave ports.
    the master device needs to assign a separate i/o pin as a cs to drive a slaves ss pin if its required. the mssp port does not provide that function.


    nice to see you have it up and running, for the record what did you have wrong earlier that stopped it functioning?
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  16. #16
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    a spi port without sdi would not be a spi port it would be something else
    IF so what would it be called , if so more of them would be handy at times i am sure - this chip has 2 ports like this , i fear that the P!0 rgb version that uses the 3 x leds ( rgb) that is specifically used for outdoor display use of >15meters view , may need 3 streams , god hope not - ill see as i have a couple on order just to find out , when china comes back on line

    i still have a way to go , with your code , i hope to get it commented well how the lib and the fonts come together with the test code for the display on the p10 so i fully understand it , which i cant say i do as yet ,

    Font char sets is needed or should say font msg sets stored in external flash is need later on , so i really hope this week to get a the displays to do something meaning full

    i still not seeing Oe, Lat working correctly , which is i think is bad port rewiring , but will know soon enough

    the main problems with interupt routines reassign to timer2 , timer 3 used a gate pin , when was not needed , setting correctly fix it, but it effected timer 1 and as such it created other issues ,

    SSP1 PPS was right , but SSP2 was not correct on the PPS originally , finally sorted that by reviewing settings, i spent a lot of time trying to make mplab -code configure to show what i wanted , which was a problem

    as it turns out this chip is doing a lot of other things ,not just getting the outputs for p10 going correctly , which is so important , rf modual , terminal services , it also doing some logging of sensors ,voltage monitoring has remote config of settings, etc

    timers 0-4 in use , 8 related INT services ,


    Anyway see how the next days progress ill send you a commented code list of what i think is happening ,so i can follow the structure design , if you can have read see if i got wrong


    Cheers

    Sheldon

  17. #17
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    i fear that the P!0 rgb version that uses the 3 x leds ( rgb) that is specifically used for outdoor display use of >15 meters view , may need 3 streams , god hope not
    if you caught my post on p10 outdoor rgb before the forum shit itself and lost a years worth of posts you would see it actually needs
    6 streams. can't repost pbp ver, it got lost when my laptop died and went to meet it maker. there was no interest shown in it either.
    i do have xc8 ver of course



    lost post talk
    http://www.picbasic.co.uk/forum/showthread.php?t=24004
    i'm surprised it got such little attention , not a good omen
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  18. #18
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    Default Re: Confirm 18f47k40 MSSP setting and allocation using PSS

    if you caught my post on p10 outdoor rgb before the forum shit itself and lost a years worth of posts you would see it actually needs
    6 streams. can't repost pbp ver,
    so you had an RGB 3 x led type on hand prior to test and it need 6 streams ?

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