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  1. #1
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    Default HSEROUT : different behaviour with 18F2685 and 18F26K22

    Hi everybody,

    One of my applications generates a 3 bytes MIDI message depending from some received data on a parallel port.
    The MIDI message is transmitted on Tx (UART1). Pin 17 of my chips.

    The program can be considered as a simple loop, waiting for the data and transmitting them if they meet certain conditions.

    I use HSEROUT for that purpose.
    My environment in MPLAB 8.92, PBP 3.1.0.4, PicKit3.

    Everything works perfectly with my old 18F2685 but when I replace it by a 18F26K22 the program hangs and the loop stops.
    When the call to HSEROUT is inactivated the loop always works correctly.

    Does anybody see a reason for which HSEROUT would behave differently with these two chips?

    MikeBZH

  2. #2
    Join Date
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    MikeSZH, Let's see the config settings and the HSEROUT statement in it's context.
    Dave Purola,
    N8NTA
    EN82fn

  3. #3
    Join Date
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    Thank you for responding, Dave.

    The CONFIG section for the 26K22 is :

    Code:
    #CONFIG
    	    CONFIG  FOSC = HSMP	    	  ; HS oscillator (medium power 4-16 MHz)
    	    CONFIG  PLLCFG = ON		      ; 4X PLL enabled
    	    CONFIG  PRICLKEN = ON		  ; Primary clock enabled
    	    CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor disabled
    	    CONFIG  IESO = OFF	    	  ; Oscillator Switchover mode disabled
    	    CONFIG  PWRTEN = OFF          ; Power up timer disabled
    	    CONFIG  BOREN = OFF	    	  ; Brown-out Reset disabled
    	    CONFIG  BORV = 285            ; VBOR set to 1.90 V nominal
    	    CONFIG  WDTEN = OFF	    	  ; Watch dog timer is always disabled. SWDTEN has no effect.
    	    CONFIG  WDTPS = 32768         ; 1:32768
    	    CONFIG  CCP2MX = PORTC1       ; CCP2 input/output is multiplexed with RC1
    	    CONFIG  PBADEN = OFF          ; PORTB<5:0> pins are configured as digital I/O on Reset
    	    CONFIG  CCP3MX = PORTB5       ; P3A/CCP3 input/output is multiplexed with RB5
    	    CONFIG  HFOFST = ON           ; HFINTOSC output and ready status are not delayed by the oscillator stable status
    	    CONFIG  T3CMX = PORTC0        ; T3CKI is on RC0
    	    CONFIG  P2BMX = PORTB5		  ; P2B is on PB5
    	    CONFIG  MCLRE = EXTMCLR       ; MCLR pin enabled, RE3 input pin disabled
    	    CONFIG  STVREN = ON		      ; Stack full/underflow cause Reset
    	    CONFIG  LVP = OFF             ; Single-Supply ICSP disabled
    	    CONFIG  XINST = OFF           ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    	    CONFIG  DEBUG = OFF           ; Disbled
    	    CONFIG  CP0 = OFF             ; Block 0 (000800-003FFFh) not code-protected
    	    CONFIG  CP1 = OFF             ; Block 1 (004000-007FFFh) not code-protected
    	    CONFIG  CP2 = OFF             ; Block 2 (008000-00BFFFh) not code-protected
    	    CONFIG  CP3 = OFF             ; Block 3 (00C000-00FFFFh) not code-protected
    	    CONFIG  CPB = OFF             ; Boot block (000000-0007FFh) not code-protected
    	    CONFIG  CPD = OFF             ; Data EEPROM not code-protected
    	    CONFIG  WRT0 = OFF            ; Block 0 (000800-003FFFh) not write-protected
    	    CONFIG  WRT1 = OFF            ; Block 1 (004000-007FFFh) not write-protected
    	    CONFIG  WRT2 = OFF            ; Block 2 (008000-00BFFFh) not write-protected
    	    CONFIG  WRT3 = OFF            ; Block 3 (00C000-00FFFFh) not write-protected
    	    CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) not write-protected
    	    CONFIG  WRTB = OFF            ; Boot Block (000000-0007FFh) not write-protected
    	    CONFIG  WRTD = OFF            ; Data EEPROM not write-protected
    	    CONFIG  EBTR0 = OFF           ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
    	    CONFIG  EBTR1 = OFF           ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
      	    CONFIG  EBTR2 = OFF           ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
    	    CONFIG  EBTR3 = OFF           ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
    	    CONFIG  EBTRB = OFF           ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
    #ENDCONFIG
    and for the 2685 :

    Code:
    #CONFIG
    	CONFIG	OSC = HSPLL
    	CONFIG WDT = OFF
    	CONFIG 	WDTPS = 512
    	CONFIG 	MCLRE = ON
    	CONFIG 	PBADEN = OFF
    	CONFIG  XINST = OFF
    	CONFIG  LVP = OFF 
    #ENDCONFIG;
    Other lines of init / config are (identical for both PICs):
    Code:
    DEFINE OSC 32
    
    DEFINE HSER_RCSTA 90h	
    DEFINE HSER_TXSTA 20h	
    DEFINE HSER_BAUD 31250               ; MIDI transmission rate
    
    spbrgh = 1
    baudcon.3 = 1
    
    PORTC = %00000000
    
    TRISC.0 = 1		
    TRISC.1 = 0	
    TRISC.2 = 0      
    		
    TRISC.5 = 1				
    TRISC.6 = 0             'TX ouput 
    TRISC.7 = 1             'RX input, not used
    I have reduced my program to a very simple test loop :

    Code:
    bsf2 :
    	gosub acquisd
    	pauseus 10
    	hserout[$90,$01,$02]
    
    goto bsf2
    acquisd is a routine which acquires the data from the parallel port (data not used here)
    For the purpose of testing, hserout only sends constants.

    In the real application the loop may be interrupted by quite rapid interruptions (every 16 s) but this does not affect the good or bad behaviour with either PIC.

    When I run the loop, the program hangs at the level of hserout. If I try to go step by step the pc stays in a small loop (0x9e, 0x10, 0x12, 0x9e, 0x10, etc )
    The hserout function in the .LIB file starts with such a short loop with the test of TXIF...

    MikeBZH

  4. #4
    Join Date
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    Problem solved !

    My fault...

    The 18F26K22 has a Peripheral Module Disable capability which allows to power only the peripherals which are used for doing the job.
    These peripherals are selected by the registers PMD0, PMD1 and PMD2. The 18F2685 does not have them.

    I have done some power measurement several months ago and totally forgotten them and PMD0 was set in such a way that UART1 was disabled.

    Now PMD0 has been properly set and everything is OK.

    MikeBZH

  5. #5
    Join Date
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    MikeBZH, What are you doing with ANSELC register? It should have bits 6 and 7 set to 0.
    Dave Purola,
    N8NTA
    EN82fn

  6. #6
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    MikeBZH, You and I were apparently responding to each other at the same time. I did not see your post before mine. The next thing I was going to mention was the state of the Peripheral Module Disable register settings. However upon power up I believe that ALL modules are enabled as I did not see any mention in the config's.
    Dave Purola,
    N8NTA
    EN82fn

  7. #7
    Join Date
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    Default Re: HSEROUT : different behaviour with 18F2685 and 18F26K22

    Dave. Yes, all the modules are enabled at power-up. I simply forgot the mods I brought to the PMD registers, lost somewhre in an other part of the code !

    MikeBZH

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