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  1. #1
    Join Date
    Feb 2012
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    Default IOC on the 27k40

    Hi guys

    The IOC options on this chip are very good , with both neg/ pos trig selection on most of the ports

    The dt_int18-34c currently does not appear the clear IOCxF bits after being trigger even if the flagreset is set
    Code:
    ASM
    INT_LIST macro; IntSource,  Label     , Type, ResetFlag?
        INT_Handler  IOC_INT, _Rx_mode_IOC ,  PBP, yes      ; Call Rx_mode_IOC subroutine for RF RX_mode
        
     endm
     INT_CREATE								; Creates the Interrupt Processor
    ENDASM
    also enable/disable of IOC " @ INT_DISABLE IOC_INT " ( PIE0.4 = 0) , will not stop the IOC interrupt being set on the IOCxF

    the triggered IOC port flag bit needs to be cleared after the interrupt is serviced - eg IOCxF.x = 0

    this what i found for my 27k40 silicon 0 ,

    but if i am wrong please check and correct me

    cheers

    Sheldon

  2. #2
    Join Date
    Apr 2014
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    Default Re: IOC on the 27k40

    First, you get a PIR0.4 generic IOCIF that's read only. Second, you also get an IOCAF/IOCBF/IOCCF.PortPin flag that indicates either an IOCAN or IOCAP type flag (since you can use either). the PIR0.4 flag automatically clears when IOCxFs = 0. With that said, you can clear the flag manually in the ISR. If you got IOCAF.2 (RA2 changed state according to your IOCAP/IOCAN Registers), at the end of your ISR add IOCAF.2 = 0 (PBP3). If you are using an ASM ISR, BCF IOCAF,2.

    "16.1 Enabling the Module
    To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated."

    That being said, we're getting more familiar with how the K40 chip & Data Sheet don't always agree. You could clear the IOCxN/P in the Register to disable IOCIE if PIE0.4 = 0 fails to work.

  3. #3
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    Default Re: IOC on the 27k40

    yes your correct, in that i could have turned off the IOC port trigger in neg or Pos , which ever was set , but the main toggling the IOC enable wont work as prev k22,k80 where it will stop the IOC being registered on k40 ,

    as i am porting code from k80,k22 where the enable / disable of IOC is in many places in code , so having to ensure the IOCxF is cleared where i am disable/ enable, this stops a not required jump to the ISR to clear it , requires a bit of work

    its just another step to do on the k40, as there is no main clear of the all IOCxF registers that i can see so far except by manual clearing,
    nor a way to ensure a globle enable / disable that ensure that IOCxF wont register a change , after being setup in the IOCxN, IOCxP triggers

    only a globle IOC status if triggered in in PIR0.4 as you pointed out in

    that said with the flag set on the which IOC was triggered in each port, and if it was negative or positive , you can have a nice branch system for each IOC or group of IOC, possible in the ISR where it was not so great in the k22, k80 IOC system

    sheldon

  4. #4
    Join Date
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    Default Re: IOC on the 27k40

    You can clear most flags from anywhere by:

    IOCAF = 0
    PIR1.5 = 0
    ...etc

    Flags for UART require reading the RC1REG to clear the flag, but they are in the exception category.

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