Hi,
If you're using the MikroE USB bootloader then the device is running at 48MHz, not 16MHz so you need to change your DEFINE OSC 16 to DEFINE OSC 48 - try it!
And here's the default PBP configuration from my PBP3 installation:
Code:
; The PBP default configuration for the PIC18F47J53 is:
;
; #CONFIG
; CONFIG WDTEN = ON ; Enabled
; CONFIG PLLDIV = 5 ; Divide by 5 (20 MHz oscillator input)
; CONFIG CFGPLLEN = OFF ; PLL Disabled
; CONFIG STVREN = ON ; Enabled
; CONFIG XINST = OFF ; Disabled
; CONFIG CPUDIV = OSC1 ; No CPU system clock divide
; CONFIG CP0 = OFF ; Program memory is not code-protected
; CONFIG OSC = HSPLL ; HS+PLL, USB-HS+PLL
; CONFIG SOSCSEL = HIGH ; High Power T1OSC/SOSC circuit selected
; CONFIG CLKOEC = ON ; CLKO output enabled on the RA6 pin
; CONFIG FCMEN = OFF ; Disabled
; CONFIG IESO = OFF ; Disabled
; CONFIG WDTPS = 512 ; 1:512
; CONFIG DSWDTOSC = INTOSCREF ; DSWDT uses INTRC
; CONFIG RTCOSC = T1OSCREF ; RTCC uses T1OSC/T1CKI
; CONFIG DSBOREN = ON ; Enabled
; CONFIG DSWDTEN = ON ; Enabled
; CONFIG DSWDTPS = G2 ; 1:2,147,483,648 (25.7 days)
; CONFIG IOL1WAY = ON ; The IOLOCK bit (PPSCON<0>) can be set once
; CONFIG ADCSEL = BIT12 ; 12 - Bit ADC Enabled
; CONFIG MSSP7B_EN = MSK7 ; 7 Bit address masking mode
; CONFIG WPFP = PAGE_0 ; Write Protect Program Flash Page 0
; CONFIG WPCFG = OFF ; Configuration Words page not erase/write-protected
; CONFIG WPDIS = OFF ; WPFP<6:0>/WPEND region ignored
; CONFIG WPEND = PAGE_WPFP ; Pages WPFP<6:0> through Configuration Words erase/write protected
; CONFIG LS48MHZ = SYS24X4 ; System clock at 24 MHz USB CLKEN divide-by is set to 4
; #ENDCONFIG
Look at the lines in bold. The PLL is enabled with a division ratio of 5. The MicroE Clicker board has a 16MHz x-tal which will result in an input frequency to the PLL of 16/5=3.2MHz where it expects to get 4MHz, the output will be 38.4MHz instead of the expected 48MHz. So even if the bootloader DOES write the CONFIG bits using the PBP default ones for that board doesn't work.
/Henrik.
Bookmarks