A/D Conversion Clock Select bits confussion ..

# Thread: A/D Conversion Clock Select bits confussion ..

1. ## A/D Conversion Clock Select bits confussion ..

Hello everyone ..

For a long time I've been struggling with these settings ... When one would like to perform an ADC reading what kind of settings he must add into his code ?

Code:
```ADCS<2:0>:A/D Conversion Clock Select bits
000=FOSC/2
001=FOSC/8
010=FOSC/32
011=FRC(clock supplied from a dedicated RC oscillator)
100=FOSC/4
101=FOSC/16
110=FOSC/64
111=FRC(clock supplied from a dedicated RC oscillator)```
So , If I'm running my PIC at 32 MHZ internal oscillator , the setting should be 011 or 010 ?

and the SECOND QUESTION :

What is the maximum ADC conversion time at 32MHZ for the PIC16F1827 ...
When I look at the conversion tables that Microchip has published for this PIC , I can't understand which is the exact time at the selected OSC frequency that takes for a complete ADC conversion time ..

2. ## Re: A/D Conversion Clock Select bits confussion ..

011=FRC tad=1.0uS to 6uS (vcc and temperature dependant)

any divider less than fosc/32 @32mhz is out of reliable conversion range

3. ## Re: A/D Conversion Clock Select bits confussion ..

FOSC is Frequency of OSCillator, so if you are using 32MHz internal osc, your fosc is 32MHz if you are using 8MHz external osc then your fosc is 8 MHz and if you are using 4 MHz external with PLL then your FOSC is 16MHz.
011 and 111 settings are for an internal dedicated oscillator with 1.6us period if I remember correct...
You can always use fosc/2 timing since faster is generally better. But again, it depends on your timing need. If you don't need a special timing, just choose whatever you like.

Edit: I'm not sure minimum conversion time but I believe it has to be larger then 10us
Last edited by elcrcp; - 19th July 2015 at 14:03.

4. ## Re: A/D Conversion Clock Select bits confussion ..

Thanks for your answers but I still do not understand something .. Which one of these oscillator settings should be chosen for a robust operation .. Or in other words , for a "classic proper" operation ... What I understand from your explanations is that I can choose any of these settings non regarding if the OSC is internal or external ...

As far as I know the Frc stands for internal oscillator ... Please correct me If I'm wrong at this point .. So If I choose 4MHZ with PLL operation , I'm running it with 32 MHZ internal oscillator which is also called the internal RC osc block , so in this case I should go with Frc for a more accurate conversion ... or with Fosc/32 or Fosc/2 for a faster conversion ... Right ?

5. ## Re: A/D Conversion Clock Select bits confussion ..

32 MHz is a too high frequency to obtain a good ADC reading. The minimum TAD is 1.6 us and If you set fosc/64 you will get a TAD of 2 us and you are barely inside the correct timing. Since you will be in the low end side as far as the TAD value is concerned. Dropping your fosc to 16 MHz with the same setting you will have a TAD of 4 us which is much better than 2 us.

Cheers
Al.
Last edited by aratti; - 20th July 2015 at 00:58.

6. ## Re: A/D Conversion Clock Select bits confussion ..

Thanks Al .. You may be right ...
Well the question is how to set the define adc sampleus parameter in pbp ? I should adjust it according to the decided Fosc ?

7. ## Re: A/D Conversion Clock Select bits confussion ..

The sampleus parameter is the time given for the acquisition ( changing the sample & hold capacitor). This timing is critical since you must charge the capacitor no more than 1T..(up to 1T the charging curve is quasi linear) Now If you have decided to use fosc = 16 MHz than the minimum pauseus you can get is 5 us so a Define adc_sampleus 15 should give you good results.

Cheers

Al.
Last edited by aratti; - 20th July 2015 at 09:02.

8. ## Re: A/D Conversion Clock Select bits confussion ..

Should we not calculate it 1.6x11 Tad = 17.6 uS ? Thus is it not better to set it to 20 uS ?

9. ## Re: A/D Conversion Clock Select bits confussion ..

The 11 TADs is the time taken by the MCU for the 10 bits convertion! Please do not confuse acquisition with convertion. The setting suggested is the time you will give to the sample & hold capacitor to charge with your input dc value. This time should be enough to charge the cap not beyond the 1T, because beyond this point the charging function is no longer quasi-linear, but totaly logaritmic.

You can set it to 20 us and see If your ADC reading are consistent and adjust this value to suite your need. (Remember that the best acquisition time will depend by the hardware setting, so every circuit has his own best acquisition time)

Cheers
Al.
Last edited by aratti; - 20th July 2015 at 12:22.

10. ## Re: A/D Conversion Clock Select bits confussion ..

Grazie tante per la risposta cara aratti ..

11. ## Re: A/D Conversion Clock Select bits confussion ..

I remember saving a link to this... http://www.edaboard.com/nextoldesttoentry1570.html
page. Be sure to hit the "next" button at the bottom of the page where there is discussion of acquisition time.

hope this helps you.

12. ## Re: A/D Conversion Clock Select bits confussion ..

I remember saving a link to this... http://www.edaboard.com/nextoldesttoentry1570.html
page. Be sure to hit the "next" button at the bottom of the page to go to Part 2 where there is discussion of acquisition time.

Possibly something of value there.
Last edited by Heckler; - 21st July 2015 at 05:13.

13. ## Re: A/D Conversion Clock Select bits confussion ..

The only part I cant understand is the line he somehow calculated 40 + 38.4 us = 78.4 uS .. where did that 40 come from ?

14. ## Re: A/D Conversion Clock Select bits confussion ..

40 us is the value the author arbitrarely gives as acquisition time "sampleus parameter".

Remember:

A too high acquisition time will give issues when the analog input approch the V(ref+)

A too low acquisition time will give issues when the analog input approch the zero

So, if you do not see any issues in your reading at the extreme of the reading field then the acquisition time used is correct!

Ciao, complimenti per il tuo italiano!

Al.
Last edited by aratti; - 21st July 2015 at 14:37.

15. ## Re: A/D Conversion Clock Select bits confussion ..

A too high acquisition time will give issues when the analog input approch the V(ref+)
A too low acquisition time will give issues when the analog input approch the zero
Where do you get this from?

The aquisition time is the MINIMUM amount of time you have to wait for the holding capacitor (and it's RC network) to fully charge/discharge to the voltage level you're sampling.

If you set the acquisition time too low then you won't have allowed enough time for the charge on the capacitor to reach the desired level, and you'll get an incorrect conversion. It doesn't matter so much if the input is near Vref or zero, it'll be wrong.

If you're measuring a DC voltage, there is no "too high" an aquisition time.

16. ## Re: A/D Conversion Clock Select bits confussion ..

Where do you get this from?
From the charging function of a capacitor!

Al.

17. ## Re: A/D Conversion Clock Select bits confussion ..

So you're saying that if you wait too long the voltage on your sampling capacitor will be wrong?

If you put a small RC network across a voltage source, what will the voltage across the capacitor be if you wait a second? A minute? An hour?

18. ## Re: A/D Conversion Clock Select bits confussion ..

You cannot use the full function because it is foundamentally a logaritmic function. For the ADC convertion you need a linear function. Once time, resistence and capacity are fixed than the charging function depend only from the voltage applied. If during the charging time you do not pass the 1T point of the function, than the charging function can be considered "quasi liner" and the system work. In other words you can deduce the value of the voltage applied. If you pass the 1T point then thing become more complicated since from that point on the function is purely logaritmic.

Cheers
Al.

19. ## Re: A/D Conversion Clock Select bits confussion ..

You're somehow mixing Acquisition time with the linearity of the ADC conversion function.

For the Acquisition time, you need the sample cap to charge to whatever value you want the ADC to convert. Period.

The time constant of an RC network is T=RC, and after one T the voltage across the cap is roughly 66% of the input voltage.
If you look at T vs percent, you get:
Code:
```1    63.2%
2    86.5%
3    95.0%
4    98.2%
5    99.3%
10   99.995%
20   99.9999998%```
If you set the Acquisition time to 1T and then convert the value, you could be VERY wrong... 37% wrong. Of course, that depends on the new input voltage you want to convert and any existing charge on the sample cap, but T gives you a worst-case number.

For example, an 8-bit ADC (1 part in 256, or 0.39%) would need an acquisition time of better than 5T, but there's nothing wrong with giving it 10T or 20T or 100T, as long as nothing else changes in that time.

You do not have to hit some magic 1T window trying to get it into a "quasi-linear" range, or guess at things to "see if it's good enough".

20. ## Re: A/D Conversion Clock Select bits confussion ..

No much to say, just keep your convintions if you are happy with them.

Al.

21. ## Re: A/D Conversion Clock Select bits confussion ..

Hi,
I must say I'm quite confused and intruiged by this statement as well.

As I'm currently messing around with the ADC in the 18F2431 I've been reading up on the acquisition time and conversion time requirement(s) in order to better understand it and I can't for the life of me find any references to issues with too long acqusition time.

The datasheet is pretty clear on the point that the conversion clock period (TAD) needs to be as short as possible, yet still longer than the minimum (418ns for 18F2431). This means that when operating at 40MHz the selection FOsc/32 must be used since that gives a TAD of 800ns. Going a step lower (FOsc/16) would violate the 416ns requirement. A conversion takes 12TAD so 9.6us in this case.

The minimum acqusition time, ie for how long the S/H capacitor is connected to the analog input before the conversion starts dependes on the source impedence driving the inputs, temperature range etc. For a 1k source impedence I calculated the minimum acquistion time to 2.38us which is ~3TAD in my case. I'm well below 1k in source impedence but I'm going to stick with a acqusition time of 4TAD.

This gives me a total A to D time of 3.2+9.6=12.8us.

Nowhere can I see any reference to issues with too long acqusition time.

Confused.....

/Henrik.

22. ## Re: A/D Conversion Clock Select bits confussion ..

if it were possible that the acquisition time could be too long then surely the optimum acquisition time would have to varied logarithmically according to the instantaneous sample voltage . the suggestion is not realistic ,unsubstantiated and unworkable

23. ## Re: A/D Conversion Clock Select bits confussion ..

Agreed.

Confused...
Don't be. You have it correct.

What you're computing is the minimum time it takes for the RC sample/hold network to charge to the input voltage assuming you're making a full-scale voltage change. Depending on the accuracy you're trying to reach that normally takes about 7T-8T. Once it's charged up (or down), you're good to go, but it does no harm in waiting longer (as long as nothing else changes).

The only thing to watch out for is if you change PIC's be sure to check the specs of the new device. The source resistance of the internal switch and the cap can be different for different families, so that can change the calculation.

24. ## Re: A/D Conversion Clock Select bits confussion ..

Henrik, I am using a rather old pic (18F2620), I still have a couple of hundreds of them. But timing apart your and mine are very similar in the setting of the TAD value and the acquisition time.
As far as TAD value is concerned I can Select value up to Fosc/64 (minimum delay required for 1 TAD = 1.6 us)
As far as ACQUISTION TIME is concerned, I have a range selectable from 2 TAD to 20 TAD. (So you have a lower and upper limits)

I made some experimenting some years ago, using the manual acquisition time, so I could increase/decrease the acquisition time beyond the 2/20 TAD limits. Unfortunatly I was not able to find these data (I have been digging for the whole day without success) but I assure you they were very interesting. The experiment was done taking 100 reading at three specific points of the 10 bits range. First point was fixed to 10 ADC count (low end), second point in the middle at 512 ADC count and the third point at 1012 ADC count (high end). These reading were taken at different acquisition time going from 1 us up to 200 us in steps of 10 us each.
Once, all the data were collected ( they have been collected via RS232 connection and loaded directly into an Excel sheet), the statistic applied were : Average/Standard deviation/standard error.
Looking at the standard error, I noticed an increase in the two extreme regions when the acquisition time was too low or higher than the 2/20 TADs region , no significant variation of standard error were observed in the middle range.
I will continue to search these files (I am sure I still have them somewhere) and If I found them I will post them here in this thread.
But everybody, with some time to spare, can repeat the experiment on his own.
Cheers.
Al
Last edited by aratti; - 23rd July 2015 at 07:11.

25. ## Re: A/D Conversion Clock Select bits confussion ..

Hi,
OK, I did the test.

For this I was using a 18F25K20 running at 64MHz and 3.3V. Vref set to VDD/VSS and measured at 2.999V.
Actual voltages measured with a FLUKE189

The test program cycles thru all the available clock selections and all the available acquisition times (49 combinations). For each selection it takes 8 readings on AN0. Between each reading it makes a dummy conversion of another (floating) channel. After 8 readings it calculates the averages and presents the result.

The test was conducted at 3 different input voltages (25mV, 1.65V, 3.285V) with 3 different source impedences (1k, 10k, 39k). For the 18F25K20 10k is the max recommended source impedence.

Here's the code if anyone wants to repeat the test.
Please note the ADC clock and acquisition time may be different on other devices, this matches the 25K20 that I used:
Code:
```'****************************************************************
'*  Name    : ADC Test.PBP                                      *
'*  Author  : Henrik Olsson                                     *
'*  Notice  : Copyright (c) 2015 Henrik Olsson                  *
'*  Date    : 2015-07-23                                        *
'*  Version : 1.0                                               *
'*  Notes   : Test program for verifying ADC clock selection    *
'*          : and acquisition times.                            *
'*          : For 18F25K20.                                     *
'****************************************************************
DEFINE OSC 64
DEFINE HSER_RCSTA 90h                       ' Enable serial port & continuous receive
DEFINE HSER_TXSTA 24h                       ' Enable transmit, BRGH = 1
DEFINE HSER_CLROERR 1                       ' Clear overflow automatically
DEFINE HSER_SPBRG 138                       ' 115200 Baud @ 64MHz, -0,08%

SPBRGH = 0
BAUDCON.3 = 1                               ' Enable 16 bit baudrate generator

ADCON1 = %00000000                          ' Vref is Vdd/Vss respectively

TRISA.0 = 1                                 ' RA0/AN0 is input
ANSEL.0 = 1                                 ' Digital buffer disabled, analog enabled

Samples VAR BYTE
ACQT VAR BYTE
RESULT VAR WORD
Accumulator VAR WORD

PAUSE 1000
HSEROUT["Start",10,13]

For ACQT = 1 to 7                           ' We have 7 different TAD settings ranging from 2TAD to 20TAD
For ADCS = 0 to 6                       ' We hace 7 different conversion clock selections
ADCON2 = 128 + (ACQT * 8) + ADCS    ' "Build the ADCON2 word by combining the two settings.

PAUSE 25

Accumulator = 0

For samples = 0 to 7                ' Take 8 samples

' First make a dummy conversion of a channel we're not really interested in
GODONE = 1
WHILE GODONE : WEND

' Then switch to AN0 and make a conversion.
GODONE = 1
WHILE GODONE : WEND

' Get the result and add it to the accumulator
Accumulator = Accumulator + Result

NEXT

' Divide accumulated result by 8 to get the average of our 8 readings.
Result = Accumulator >> 3

' These selections matches the 18F25K20
CASE 0
HSEROUT["FOSC/2     "]
CASE 1
HSEROUT["FOSC/8     "]
CASE 2
HSEROUT["FOSC/32    "]
CASE 3
HSEROUT["FRC        "]
CASE 4
HSEROUT["FOSC/4     "]
CASE 5
HSEROUT["FOSC/16    "]
CASE 6
HSEROUT["FOSC/64    "]
END Select

SELECT CASE ACQT
CASE 1
CASE 2
CASE 3
CASE 4
CASE 5
CASE 6
CASE 7
END SELECT

' Report the result.
HSEROUT["  Result: ", #RESULT, 13]

NEXT
NEXT

PAUSE 100

END```
And here are the results:
Code:
```*****************************************************
*****************************************************
VRef is VDD/VSS measured to 3.299V
1k resistor in series with input
*****************************************************
*****************************************************

Input voltage 25.7mV

Input Voltage: 1.650V

Input Voltage: 3.286V

*****************************************************
*****************************************************
VRef is VDD/VSS measured to 3.299V
10k resistor in series with input
*****************************************************
*****************************************************

Input voltage 25.7mV

Input voltage 1.650V

Input voltage 3.286V

*****************************************************
*****************************************************
VRef is VDD/VSS measured to 3.299V
39k resistor in series with input
*****************************************************
*****************************************************

Input voltage: 25.7mV

Input voltage: 1.650V

Input voltage: 3.286V
I haven't analyzed any of it yet and I don't have any more time just now but I wanted to post the results. If anyone wants to graph the results in Excel or whatever to better see what's going on, please feel free to do so.

/Henrik.

26. ## Re: A/D Conversion Clock Select bits confussion ..

You certainly coverted all the bases! Good job.

Instead of bothering to graph all the data and try and make sense of it, Let's start with this:

The 25K20 has a TAD spec of 0.7us min.

At 64MHz, that means all ADCS settings except for FOSC/64 and FRC violate minimum times (Table 19-1).
Using the FOSC/64 setting gives a TAD of 1us

Computing Tc from equation 19-1 for each of the three source resistances gives:
1K = 0.27us
10K = 1.2us
39K = 4.2us

Computing TACQ = Tamp + Tc + Tcoff, given Tamp = 5us and Tcoff = 0 (25degC) produces:
1K = 5.27us
10K = 6.2us
39K = 9.2us

So, since TAD = 1us, TACQ must be a min of ~6-9 TAD for the three different resistances.

Removing all of the measurements that don't fit the above you get:
Code:
```*****************************************************
1k resistor in series with input (TACQ=5.27us)
*****************************************************
Input voltage 25.7mV

Input Voltage: 1.650V

Input Voltage: 3.286V

*****************************************************
10k resistor in series with input  (TACQ=6.2us)
*****************************************************

Input voltage 25.7mV

Input voltage 1.650V

Input voltage 3.286V

*****************************************************
39k resistor in series with input  (TACQ=9.2us)
*****************************************************

Input voltage: 25.7mV

Input voltage: 1.650V

Input voltage: 3.286V
Pretty consistent. It shows that waiting longer than the minimum doesn't get you anything, but it also doesn't change anything either.
The interesting thing is as you look through the raw data you can see the effect of not using the proper TAD setting for the clock freq you're using, or not waiting/setting TACQ to at least the minimum time.

27. ## Re: A/D Conversion Clock Select bits confussion ..

it might be interesting to connect the "dummy conversion" pin to ground and then in another pass vcc , and give it a long acquisition and then take your reading . I would expect the real effect of a too short acquisition time would become more evident (ie the previous reading sample cap charge will have a effect on the current reading)

28. ## Re: A/D Conversion Clock Select bits confussion ..

I wondered about that too. As you say, connecting it to a floating input would probably just leave the charge on Chold since all you have is the leakage current to discharge it.

I noticed in figure 19-4 that they show a 2TAD "discharge" time between measurements, and they say this:
19.2.3 DISCHARGE
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged after every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
The PIC18 reference manual has the same sort of text, but is also has the statement
The charge holding capacitor (CHOLD) is not discharged after each conversion
so it sounds like they're talking about something to do with the internal ADC structure and not Chold.

It WOULD be interesting to see the same measurements without any averaging and with alternating input voltages for the in between "idle" cycles.

29. ## Re: A/D Conversion Clock Select bits confussion ..

Hi guys,
OK, doing a dummy conversion on a floating input wasn't the greatest idea....

I took out the averaging and set up my arb gen to generate 3.3Vpp noise and injected that into AN1 (the dummy channel).

Code:
```25.6mV input, 10k source resistor, 3.3V noise on "dummy channel":

***************************************

3.285V, 10k source resistor 3.3V noise on "dummy channel":

Then I connected the dummy channel to GND:
Code:
```25.6mV input, 10k source resistor, "dummy channel" connected to GND:

*******************************************************

3.285V input, 10k source resistor, "dummy" channel connected to GND:

And finally, dummy channel to Vdd (3.3V):
Code:
```25.6mV input, 10k source resistor, "dummy channel" connected to Vdd:

*********************************************

3.285V input, 10k source resistor, "dummy channel" connected to Vdd:

Henrik.

30. ## Re: A/D Conversion Clock Select bits confussion ..

Thanks Henrik. So again, removing the ones where the ADCS setting is invalid/too fast gives:
Code:
```25.6mV input, 10k source resistor, 3.3V noise on "dummy channel":

*********************************************

3.285V, 10k source resistor 3.3V noise on "dummy channel":

*********************************************

25.6mV input, 10k source resistor, "dummy channel" connected to GND:

*********************************************

3.285V input, 10k source resistor, "dummy" channel connected to GND:

*********************************************

25.6mV input, 10k source resistor, "dummy channel" connected to Vdd:

*********************************************

3.285V input, 10k source resistor, "dummy channel" connected to Vdd:

Probably the ones of most interest are where Chold has to swing the full range between samples:
Code:
```3.285V input, 10k source resistor, "dummy" channel connected to GND:

*********************************************

25.6mV input, 10k source resistor, "dummy channel" connected to Vdd: