Multi CPU , design and interrupt control

[longpole001]

Hi guys ,
i am starting on the design of 2 or more cpu's and how the design the interface between the cpus / flow control , and control word , data interface software

it is likely that each cpu will control 3 or more fuctions each off their respective pins
I am assuming 1 of the cpu's will be the master with the others being the slaves connected via the SPI bus

Each cpu will have an interrupt pin assigned and connected to the IOC on the master , which will notify the master that data needs service

the master will use a select line connected to each cpu to allow use of of the spi common bus

in the design of the interface between the cpu's , the interface software will have control word / data arrangement where master will arrange the flow.
even if say cpu 3 need the data it will be resent via cpu1 at this point , i think i ring system may be better but not sure how to control it ???

comments on how you guys have done this well for a complicated multi cpu with interface management arrangement would be a good guide


cheers

Sheldon

[HenrikOlsson]

How about a shared memory setup?
Each device could be allowed a certain timeslot (10ms, 50ms, whatever is needed) to access the memory in a circular fashion.
Each device can read what it needs and write what it needs.
Each device could have a dedicated status or "what to do" byte in the memory. When any device want Another device to do something it writes to the "what to do" register for that device. Each time a device is allowed access to the memory it reads the byte and acts accordingly.

/Henrik.

[BobK]

Hi Longpole 001,
Back in 2005 I built 2 160-Input annunciator panels using 20 - 16F74 chips "talking" to a 18F452 on the master board and 20 - 16F872 chips talking to another 18F452 master. I used 1 line for the "talking" and 1 line for a busy indicator. The 18F452 was doing various tasks while also checking the busy line to see if any of the 20 boards had data for it. As soon as it sensed a low on the busy line it stopped whatever it was doing also made the busy line low and kept it low until it was done handling the data before resuming its tasks. The boards would wait for 10ms after sending its data before resuming its tasks. The systems have been in service since the fall of 2005 and have been working fine since. The master board also sends a report to a printer for a hard copy record of events. I had planned a series of upgrades to the systems including an periodic message from each of the 20 boards indicating the boards were there and working. Any board not responding to the interrogation after a couple misses would then cause the master board to send an alert to the people working in the office. I have also started building a smaller system using RS485 as the means of communication with several more features added to the system.

Does this sound like something you are looking for? Let me know.

BobK

[BobK]

Hi Longpole,

I hope I didn't waste your time but I had not read your previous post on your project but I just finished reading all of the replies. Boy you really have your hands full. I will keep and eye on your progress and best of luck to you!
BobK

[longpole001]

thanks for the insight in to your project,

my current project is getting large and although i am reviewing distribution of functions , some are more complex than i first thought , the code is likely to get to 256k over the next year of updates and development .

my current goal is to make the first revision work ok with min required fuctions and by about late march have the 2nd revision pcb , with the 2 cpu design / interface code started

The key is the interface and the code overhead ,

ill post a drawing of the planed interface , but basicly a spi with 2 software controlled pins , 1 out for interupt request, and 1 for cpu chip enable for spi control per cpu, the interface software will setup a control code and data arrangement with so many bytes in a buffer swap arrangement.

a common memory access and higher subroutine access command structure on the master for the slave access is currently in my mind. with this common base the cpu count can be increased easly and allow for lot more code space as fuctions expand.

ill try and get the pre design done in the coming weeks


cheers

Sheldon

[Demon]

Sheldon,

If your project might grow that much, you might want to consider adding unused PICs on your network for future distributed processing.

It's easier to have a chip sit idle on a board than ask users to open a product and add an expansion board (even that could be something to consider).

Robert

[longpole001]

that might be a good consideration