when 128k is not enough

[tumbleweed]

Thanks for the updated info. Interesting idea about using SRAM and serial flash for 0 wait states.

this method on surface may allow for the expansion of available ram to the PIC as well

It would, but you're limited to accessing it using TBLRD and TBLWR instructions, so it wouldn't function as "normal ram"

The points highlighted in the thread indicate that the generated hex file would need be edited at the 128k code boundary , sub divided into 2 hex files manually, then loaded in to the PIC program area , then into external flash , then from external flash into the sram for use at startup

You'll likely have to have a bootloader anyway to read/write the serial flash, so you could just have the bootloader handle the whole hex file without having to manipulate it. Store the entire thing in serial flash, and then at power on read the data and either program the internal flash (for the first 128K) or copy it to the SRAM (for the rest). After doing that once, you wouldn't have to reprogram the internal flash unless things change.

[longpole001]

yes splitting up into 2 cpus is no fun either , its a lot of work and cost either way, using EMb looks easier to implements if the codeing can be done ok , another issues is the amount of i/o ports the emb takes ,

the i/o ports cant really be used for anything else except the eMB bus, cos even if the ports / normal cpu i/o while not using the emb , any code that runs in the emb and requests hardware connected to pins that are emb bus wont work