All about Occillators? Frequency/PLL?

[wdmagic]

OK Im getting confused again. Ive been working with internal OSC for awhile, and i have done just a basic 4mhz resonator, and a 20mhz ttl osc. however I would like to get to understand more how the OSC's are chosen and used, for instance, say you have a 18F4550, it has a usb option and reading a bit on the notes the usb needs to run at 48mhz for full speed use. now do you have to use a 48mhz crystal or ttl or can you use say a 12mhz and use a div/4 option??? I havent messed with the pll or div stuff, I need to get an explanation of how you get multiple frequencys by changing options on the chip, and does the cpu of the chip still run at the actual crystal freq. ??? can you run a 4550 chip faster than 48mhz?

Someone point me in the right direction, oh and what would be the normal advantage of going with a higher freq crystal ?

[mackrackit]

This should help
http://www.picbasic.co.uk/forum/show...8359#post68359

[wdmagic]

ok that got me even more confused
4mhz with a pll of 1 = 48mhz??? seems backwards
i thought it would be something like pll splits the freq into divisions so a pll1 would be no split
but 2 would double the freq.

[mackrackit]

I is not about math but about how the register is selected. Take a look at the data sheet, it has a nice graphic.

[rsocor01]

ok that got me even more confused
4mhz with a pll of 1 = 48mhz??? seems backwards
i thought it would be something like pll splits the freq into divisions so a pll1 would be no split
but 2 would double the freq.

Ok, let me get you even more confused . This is probably the graphic that Dave was referring to. Follow the red arrows that I drew.



And this is from the datasheet,

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.

[Charlie]

Think of a PLL as a sort of frequency multiplier. It is actually a free running oscillator that is synchronized to an source at a lower frequency. The high frequency oscillator output is divided by an integer value and compared to the low frequency reference and the difference in when they both cross zero (the phase) is used to move the higher frequency slightly higher or lower - hence the name Phase Locked Loop. Clear as mud?

[wdmagic]

yes I think thats part of what was getting me confused, PLL is a frequency multiplyer however it shows division symbols in the graphic, I was thinking that the PLL divided the input frequency.

[Art]

It doesn't take anything so fancy as a PLL to divide a frequency,
you can make a flip flop out of two transistors to divide by 2 for example,
and with a chip that contains four of them there are many more options.

[wdmagic]

OK so let me get this strait.
If I have a 4550 chip with a 4mhz crystal attached, If I set PLL to divide by 5, then I would need to set DEFINE OSC 20 ?

Folloing the red arrows in the previous response, that takes you to usb frq, now say I follow downwards to CPU divide. I have a option to set the CPU divide, but what doeas that do? does it act like a secondary PLL and increase the freq even more?

going with my example above, if I set the CPU Divive by 2, would that make a 4mhz crystal into a 40mhz? and DEFINE OSC 40 ?

is there a hindrance in using PLL and CPU div, a reason you would not want to use it? other than crystal cost is there a benefit to using it?

[HenrikOlsson]

Hi,
I've never used USB (tried once, couldn't get it to work) but here's my interpretation of the figure in the previous post.

If you connect a 4MHz x-tal to the PIC you need to set the PLL-prescaler (PLLDIV) to divide by 1 (PLLDIV=000) because the 96MHz PLL expects 4MHz input in order to generate 96MHz output - it even says 4MHz input only. Had it been a 8MHz x-tal, you'd set the PLL prescaler to divide by 2 in order to feed 4MHz to the downstream PLL circuitry. Note that you are indeed dividing the input frequency in order to get the needed 4MHz input to the PLL which is THEN multiplying that 4MHz signal in order to get 96MHz.

The 96MHz output signal from the PLL is then divided by 2 to generate 48MHz that can be used for the USB peripheral provided USBDIV=1 and FSEN=1. So far we haven't really touched the CPU clock....

Now you have the option the derive the CPU clock from the 96MHz signal by using the PLL postscaler (ie set your CONFIG to XTPLL mode etc) OR "directly" from your 4MHz oscillator by using the Oscillator postscaler (ie set your CONFIG to XT or HS mode etc).

If you use XT mode you'd set the Oscillator Postscaler to divide by 1 and DEFINE OSC 4 (that's the maximum you can get that way). If you use XTPLL mode you could, for example, set PLL postscaler to divide by 2 and DEFINE OSC 48.

That's how I read the schematic, I'm open for corrections!

/Henrik.

[Charlie]

Absolutely correct, Henrik and a nice clear explanation - at least that's how it seems to work in the projects I've done. The PLL does a fixed multiply by 24. PLL's can distort the shape of the square wave coming out of them (the high time might be different than the low time) so you make it run twice as fast as needed, then divide by 2 afterwards to make the shape nice and symmetrical again.

[wdmagic]

ok I think I got that part now as it relates to the USB section, what about if your not messing with USB at all though and you want to run your chip at a higher frequency than the crystal your using, say I have a 4mhz but I want my chip to run at 20mhz. is that possible, or am I supposed to be using CPU DIV for that and get 16mhz? or would I have to just start with a large freq crystal and just downgrade its freq. thats where im getting confused. I have many 4mhz &8mhz crystals and a single 20mhz, and a couple of oddballs that are not suitable for pics. I can order 48mhz ones though if I need too.

[HenrikOlsson]

Hi,
The only way to increase the frequency (on this chip) is to derive the CPU clock from the 96MHz PLL by setting the OSC CONFIG to PLL mode. For this to work you must ensure that the x-tal frequency you're using is able the be divided down to 4MHz by any of the available PLLDIV ratios, 4MHz is fine. You then have an internal 96MHz clock available and possible dividing ratios of 2, 3, 4 & 6 giving a CPU clock of 48, 32, 24 or 16MHz respectively - no way to get 20MHz that way.

If you want to use your 8MHz x-tal, same as above but now you must set PLLDIV to divide by 2 in order to feed 4MHz to the 96MHz PLL. The rest would be exactly the same.

If you "must" run the CPU at 20MHz then use a 20MHz x-tal and use normal HS mode instead of PLL mode for the OSC CONFIG.

/Henrik.

[wdmagic]

ok now I get it, that makes so much more sense now. thanks so much.

[mackrackit]

Another nice thing about using a 4MHz x-tal and PLL'ing up to 48MHz is it can be done at 3.3 volts. If you were wanting to run the same chip at 48MHz with an x-tal you would need 5 volts.