Sine wave power inverter

**mincing** · - 23rd July 2007, 06:38

Dear Sougata,

It was a great help indeed.

C-sinewave has lots of info.

However I would like to know little back ground.Thewre are three tables used ,one for sine wave,one reference sine wave and one error/delta correction.I was not able to understand how he arrive at those tables and the values in the tables.Little more deep in to back ground would probably a great help.

thanks very much,

**mincing** · - 23rd July 2007, 06:41

Also I would like to know what is the nominal DC volatge used.in that scheme.

**sougata** · - 26th July 2007, 03:48

Hi Mincing,

I am sorry I need to put some time and scratch my head to explain the C code. Currently I am a bit involved in some projects (pulling my hair almost always

) But here is a crude explanation.

For a simple proportional control system the PWM for the sinewave for the current pointer is looked up and the previous PWM is used with the feedback to determine the error. Thus before the current PWM is made through it is corrected for errors by proportionally modifying it.

Since for your system the max PWM is 255 (8bits) you cannot scale it up any more so your maximum gain is 1.0. Means your hardware should be able to step up the voltage and provide the current at maximum load, minimum permitted input supply. Now what we found in using the 16F is that the multiplication routines were not fast enough (18F has got a hardware multiply) to be calculated on the fly and still leave room for other tasks such as AC Restore Sense (F/V permit), Batt-low sense (+ Indication), PC communication, Overload (Thermal/Power) and Fault sense. So what we did was implement a pseudo hardware PWM. We used the compare in 16 bits and used the High Byte from the sinetable and lowbyte from the error computation. Now we find that PWM results are unsatisfactory. So we decided for lookups table that contains some precomputed results for current and voltage. This speeded up the whole thing but we lost resolution. However for a domestic inverter it was acceptable as the regulation were within specs. I am sorry I cannot reveal any more details.

So far you have not posted any codes and thus I cannot help you on your code.
We (Me and Pramod) are planning for a dsPIC based inverter for the next season and if that happens as a reality then we may release the old code to public. No promises however at this moment.

Best of Luck

**mincing** · - 27th July 2007, 09:36

Hope you are fine.

Thios time I have come up with a weird question.What is the meaning of Sine PWM being 25KHz.

Say we consder 32 samples it gives ,20ms/32=625uS.
===>frequency of each sample is only 1.6KHz .

Then ecverybody talks of 25 KHz .Could you please explain that a little.

Thanks,

**sougata** · - 27th July 2007, 10:37

Hi,

You are using a lookup table to modulate a carrier frequency (The PWM). In analogue world this is AM. But the pronciple here is of a class D amplifier. That is your switches are either off/on and not working in the linear region. You can use any frequency thats twice (nyquist) the output frequency mulitplied by the resolution (steps) of the lookup table. Your output transformer and parallel resonant capacitor forms a filter to integrate the modulated PWM into a sinewave. Normally the PWM is kept higher than 20KHz to reduce audible noise in the transformer. While keeping it lower has a certain advantage of lower switching loss.

sanjay_9991 · - 24th August 2007, 20:23

if any one willing to share pic based sinewave upscum inverter design can plz contact me

**walkura** · - 17th October 2007, 20:59

I was reading the posts in this topic and maybe i'm a bit late with my reply ,but i just found this forum .
The flux imbalance problem i saw mentioned before is something i know from smps designing .
Especialy in transistor push pull it can be a nasty subtle failure (with mosfets you have this problem already a lot less but i get back to that) .
The essence of flux imbalance is this you start at the 0 Gauss point ,gate 1 opens mosfet1 for x time transporting an amount of charge of x (m)Joule inducing a magnetic fieldstrength of x Gauss in you're core (depending on the frequency usualy between 1200 to 2000 +-) .
When for some reason there is a difference in
A : timing (Volt-second imbalance) better said (pulse 1 is shorter/longer then pulse 2 (technicaly impossible with 3525 etc. but homebrew program's might have different idea's)
B : while making you're ferrite you wound more on 1 of the windings .
In either of these cases pulse 1 will create a certain amount of Gauss and pulse 2 is not making exactly the same amount magnetic fieldstrength (youre core doenst get as much Gauss down as it went up).
The result is that you're core slowly accumulates that little remainder of fieldstrength after a x amount of pulses it runs into the flat part of the curve the core is so called saturated and according to Faradays law it can't support the magnetic field you're induction (ac resistance) drops to almost 0 Ohm destroying you're transistors .
From what i saw everyone here used mosfets ,in this aspect it suprises me a little you mention fluximbalance .
A normal transistor has a negative temperature coeeficient (this will increase the destruction speed in imbalanced transformers)
Mosfets however are the opposit when you have a imbalance one mosfet gets warmer its resistance increases and amount of joules delivered to the coil(core) go's down .
I hope this explained in normal human words the concept of flux imbalance .
For the people that want the more in depth story i would advice read the book from pressman called switch mode powersupply design .
This book offers in relative understandable language the concept and theory on +-15 topology's (not to mention good chapters on magnetics ,feedback & gatedriving etc. etc.)

Last summer i tryed a pwm sine inverter but lack of time froze the project for now .
Although i did have it working low power it never came out of experimental fase.
You may call me nuts but i did it with a st7lite25 + pushpull stage ,second order chebchev filter.
Next round will be sg3525 (for generation of 500 watt +- 310 volt) sync. rectification ,half bridge pwm stage + lc filter like you would expect in a class D amplifier .
(my last setup worked very well in low powers but what with 500 or 1000 watt ,how to filter?)

Good luck with youre inverters everyone

**sougata** · - 18th October 2007, 06:38

Hi,

That was a great explanation walkura and thanks for the "human" explanation. Now I would try to dig into the software aspects a little. I am a complete self taught and know my lackings, so please correct me if I am conceptually wrong.

While changing cycles within the software the loop latency may be variable if you are not using your own asm interrupts to deal with that. Since this is all about PBP my recommendations are for time critical routines use asm. As already proved asm+PBP=muscle. Considering a round-robin multitasking with no blocking codes would ensure specific time slots alloted to different routine on priority basis.
Your load is imbalanced. I have seen a few cheap soldering irons which has a single diode inside them. Causing to draw current in only cylce.
For ease of manufacturing I have seen MOSFETs on a common heatsink. This reduces a per channel MOSFET Rds-On difference and thus should be avoided for a stable design and utilize the MOSFETs property of negative temperature co-efficient for balancing.
Per cycle flux reset may be applied during the dead-time with its own pros-cons (may not be applicable for ZVT implementation)
Since the current drawn per cycle is also a function of the impedance it may be accomodated in software as well as almost all hardware designs support current sensing.
Sometimes ADC based current sensing can take longer to come into action and kill your MOSFETs. So my advice is use a comparator based sensing to quickly turn-off your MOSFETs under fault conditions and use the current sense for your other tasks or PID.
If you are into serious intelligent smps design then consider the dsPIC (No PBP support however). Your tasks become real easy for only smps implementation.

**mincing** · - 12th November 2007, 09:15

Hi all,
NOw I have completed quite a bit.yet there are two issues that are still dogging me.
1.Output stabitity,
2.Heat at no load( the power dissipation)

The output sine wave is quite stable as long as the system does not enter the closed loop.
Once it enters there is a continuous up/down swing of out put voltage and sine wave.

We could control it to quite a bit by putting a PI controller before the feed back.
still there is a fluctuation of about5 to 6 volts.

2.heat is toomuch.the no load currnent of the unit is 2A at 24V and when added with more during loading,i am afraid I can run unit like this.
any suggestions are welcome!

**sougata** · - 19th November 2007, 14:01

Hi Mincing,

Sorry for the late reply. I really do not get time (or get into weired problems) to log into this forum. Without specific details about your circuit like schematic, code it is impossible to suggest anything.

**mincing** · - 20th November 2007, 09:30

I had posted shchematics in the past and we had even discussed it in the forum.

**sougata** · - 20th November 2007, 14:23

Dear Mincing,

You reported heating. Without actual values of components and detailed circuit diagram it is very difficult to guess whats going on inside. Also if you are using de-saturation protection schemes as used in IGBTs your MOSFETs may heat up if not designed carefully. And without code it would be not possible to find out if it has got something to do with. Anyway I would be out of station for somedays and would check back later.

**mincing** · - 27th December 2007, 14:04

can you help me how to calculate snubbers for H-bridge inverter mosfet switches.

suggestions from any are welcome!

**walkura** · - 28th December 2007, 17:14

Good evening Mincing .

I seen your question about snubbers and can copy-paste you a relative simple answer .
But i have to add that this is a dissapative snubber (i'm not always happy with that ,but it solves the ringing)
The information that follows is from the website of ridley engineering (they give a clear calculation method)

If you have any ringing waveforms in your power circuit, these waveforms must be damped or they can lead to device failure, excessive EMI, or instability. In many cases, you can damp a ringing waveform with a series RC network across the offending device.

Note: if the ringing frequency is not almost two orders of magnitude higher than the switching frequency, you may be in trouble. It will be hard to damp the ringing without excessive dissipation, and alternate circuit solutions must be found.

First, you need to measure the natural frequency of the ringing waveform.
To design the snubber for the power FET of a flyback circuit, for example, first run the circuit at low power with an oscilloscope probe on the drain waveform with no snubber.

Make sure you are using a low capacitance scope probe, otherwise the waveforms will be modified by the connection of the probe. If you suspect that the probe capacitance is too high, just set the scope to a higher sensitivity, and without making electrical contact to the FET drain, just bring probe close to the device. You will see the high-frequency ringing waveform due to the radiated noise.

Observe the ringing waveform at turn-off on the drain. Use a reasonably high input voltage (without destroying the FET, or course) since the resonant frequency of the ringing will be voltage dependent. Record the resonant frequency.

The ringing is caused by an equivalent RLC network. For a low-loss circuit, it will be quite undamped, and the oscillations will continue for many cycles. Step 1 is to add a damping R across the device. First , you must know one of the resonant elements, L or C. On the primary switch, the leakage inductance is the dominant L, and should be well known. For a secondary ringing, the diode capacitance will be a known quantity.

Calculate the characteristic impedance, of the resonant circuit.

If you know L, Z = 2 x 3.14 x f x L

If you know C, Z = 1/(2 x 3.14 x f x C)

Try an initial value of snubber resistor of R = Z. This usually suffices to control the ringing.

Using just a resistor across the power device will control the ringing, but the dissipation would be very large. A series capacitor is used to reduce the power dissipation in the damping resistor.

Calculate the C needed in series with R according to: C = 1/(3.14 x f x R)

Increasing C beyond this value will increase dissipation, but will not improve the damping. In some cases you will be able to decrease it by 30% or so, but any less than this and the snubber will be less effective.

Size the resistor according to the dissipation it will see: P = C(VxV)Fs

where V is the voltage on the device when it is off. Depending on the circuit operation, the actual dissipation may be closer to half this value in some cases, and the design will be conservative. Use thermal data from your circuit to determine if the resistor size can be reduced.

Build the snubber (keep leads short) and test the circuit. You should be close to the final solution on this first attempt.

If the problem remains ,i would advice you the book switchmode powersupply's by Pressman .
They have a chapter on all sort of snubbers (active passive etc. etc.)

Good luck Walkura

**mincing** · - 31st December 2007, 07:17

Thanks a lot for the reply,Walcura.

However I can manage snubber calci for Flyback and other SMPS.My problem is with inverter H-bridge snubbers.
Please give any info. if you have or find somewhere.

regards

**Pranav Verma** · - 16th March 2008, 11:44

[QUOTE=sougata;35864]Hi,

I am devloping a proogramm for inverter,but i need some helps, More over i have devloped the programm on theory.but in practical i have some problem

i have genrate 50 Hz frequency by a loop and delay.Out Put is Ok but when put load about 100 wats on it
the output voltage go down more tahn 40 volts.

Please help me to do it in write way, I am the lerner and new in the are of pic programming.

Please helps me

**sougata** · - 16th March 2008, 12:49

Hi,

You need to modulate your sinewave according to a modulation index (that increases decreases the output voltage) derived from the error. Inititally a proportional error scheme is okay to experiment with later can add up to PID. In addition you can do a point by point correction to lower distortion. In 16Fs multiply is not supported in Hardware thus a different approach may be taken. Use a sliding lookup table. Here you have more number of points in the lookup table than regular 32/64 points. However it should be a single quadrant lookup table. Now if the resolution of the lookup table is increased you can have a sliding index (according to error) to have voltage correction without much software overhead.

**babalola** · - 12th May 2008, 13:23

since no one would review my c-code on this subject, ih have decided to modified suogata bacis code on sine wave inverter thread. i am using PIC16F72 for the evaluation because that is the processor that is readily available with me now.

The picbasic iam using is the pro demo version and so i appriciate that i can't run a code more than 31 command line.however upon trying to compile the code ,the following erros are reported:

1: Error line 116 :redefinition of label T0CON

2: Error line 119: bad expression

3: Demo limit of 31 command line exceeded (this is understood)

pls, can any one fix these problem for me?.

(a): With the way the modified code stands,can it generate two complimentary sine pwm signals DRIVE1& DRIVE2?.if yes how do i include a delay routine of about 470ns for dead-time control between the two signals?

(b): If the code cannot generate the two complimentary sinepwm signals what do i do to fix the stuff?.

regards,
babalola.

**sougata** · - 12th May 2008, 14:25

Hi Babalola,

The routine I posted uses the FSR0 indirect addressing method which is not available in the 16F72. 16F72 has a single FSR register so it would be a different implementation. With Anded outputs steering the PWM should not be difficult. You can use the same phase drive signal to drive the upper MOS so only the lower MOS would be switching with your PWM.
With 20MHz clock each of your instruction takes 200nS. So servicing the interrupt, (All MOS turned off within it) and then fetching the lookup table from PBP and switching as per system flag is quite some DEAD TIME . Another way of steering the PWM is using Four Buffers each connected to individual PIC ports and 4 nos of 4.7K resistors from the PWM pin to the four ports. So you get the following output;

1. PORT pin floating (Z, as input) = PWM
2. PORT pin LOW = LOW
3. PORT pin high = High

Since you are using a demo version of PBP, I would try to find some time to get some portions compiled for you. However I am a bit stuck and behind schedule in one of my projects. So please hang on...

Anybody else out there to help... Please do.

**babalola** · - 13th May 2008, 15:53

I have found that 16f72 has only FSR(at addr. 04,84,104&184h).from the datasheet,could that be the reason for the errors?.implementing this seems a tedious task for me as a beginner in basic and i need further help. can't the anded schematics attached to my last post do the steering?. from what i understand by using four ports with buffers to steer the PWM would mean configuring the four ports as input permanently, is it? i will appriciate the compile portion so that i can use scope to verify the PWM outputs.

babalola.

**sougata** · - 13th May 2008, 18:11