Error when compiling with DT_INTS_3_4b"

[longpole001]

the IOC had the reset done in it prior, as i have had issues with that on the 27k40
, but timer1, timer0,RX2 did not have any resets and were ok before they went to low priorty ISR

[tumbleweed]

That's odd... I don't see anything different about TMR0 or TMR1 in the file I have.

There's no point in trying to clear RCxIF... that bit is read-only and will be set as long as there's a character in the receive FIFO. The only way to clear it is to read RCxREG.