Changed the registers one more time - still no PLL lock being reported.
Below:
Code:
RF_Init_Values[0] = $2A 'Standby mode, 915-928 MHz, VTune by inductors, ENABLE R1/P1/S1
RF_Init_Values[1] = $8C 'FSK, max IF gain, Packet Mode
RF_Init_Values[2] = $03 '100KHz Freq Dev
RF_Init_Values[3] = $07 '25kbps
RF_Init_Values[4] = $0C 'for OOK mode, not apliable
RF_Init_Values[5] = $01 '16Bytes FIFO, 1 byte threshold FIFO interrupt
RF_Init_Values[6] = $77 '915MHz R1 Reg
RF_Init_Values[7] = $64 '915MHz P1 Reg
RF_Init_Values[8] = $32 '915MHz S1 Reg
RF_Init_Values[9] = $74 '920MHz R2 Reg
RF_Init_Values[10] = $62 '920MHz P2 Reg
RF_Init_Values[11] = $32 '920MHz S2 Reg
RF_Init_Values[12] = $38 'config mode for OOK, not apliable
RF_Init_Values[13] = $00 'RCV:IRQ0=payload ready + IRQ1=CRC OK
'TX: IRQ1=TXdone
RF_Init_Values[14] = $01 'FIFO starts filling when SYNC detected,TXDONE goes hi when done,
'RSSI IRQ when is above level set, enable PLL lock
RF_Init_Values[15] = $00 'RSSI interupt level zero - minimum
RF_Init_Values[16] = $A3 'default filters config
RF_Init_Values[17] = $38 'default filters config
RF_Init_Values[18] = $30 'sync word ON, 24bits, 0 errors tolerance
RF_Init_Values[19] = $07 'reserved reg
RF_Init_Values[20] = $00 'RSII status read register, 0.5dB / bit
RF_Init_Values[21] = $00 'OOK config reg
RF_Init_Values[22] = $53 '"S" 1st byte of sync word
RF_Init_Values[23] = $53 '"S" 2nd byte of sync word
RF_Init_Values[24] = $53 '"S" 3rd byte of sync word - my initials!
RF_Init_Values[25] = $53 '"S" just in case
RF_Init_Values[26] = $72 'Cutoff fcy = 200KHz, output power = 13dBm 0b000
RF_Init_Values[27] = $3C 'clk out disabled - default 427KHz
RF_Init_Values[28] = $03 '3 bytes payload
RF_Init_Values[29] = $01 'initial MAC ADDRESS, only for test
RF_Init_Values[30] = $5E 'Fix Packet Lenght, 3 bytes preamble, whitening ON, CRC ON, Node ADDR|0x00|0xFF filtering
RF_Init_Values[31] = $00 'FIFO autocreal enable if CRC fails, Write to FIFO in stby mode
I'm frustrated ......
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