Hi Richard,
Thanks for your time in looking at this. I am using a scope so 10 mS is very visible. I use the melabs U2 USB programmer and manually set the config fuses as per the table at the top of my program. I force all pins to be digital via the ADCON1 statement ADCON1 = %00001111.

In the attached code, I have followed your advice and loaded the device reference file then removed the ';' character where appropriate to activate that line. Still no joy, nothing on the ClkOut line or the LED lines. Reset is pulled high by 1k to 5V and there is +5 to both Vdd pins.

I have 3 spaces before #CONFIG - is this acceptable or must #CONFIG appear in column 1

#CODE
data @0, "Wet ver b 3 Nov 2013 "
'Internal 8 MHz clock. INTIO1 Internal Oscillator with FOSC/4 output
'on RA6 and I/O on RA7.
'******************* Configuration fuses ***************************
' Device = PIC18F4620
' Osc = INTIO1 (ClkOut), FSCM = En, Int Ext Switch = En, PwrUpTmr = En,
' BrownOut = Dis, BrwnOut Volt = 2, WDT = Dis, WDT PostScaler = 512
' CCP2 on RC1, PortB Rst = Digital, LowPwr Tmr1 Osc = Higher power,
' MCLR = Reset, Stack Over/Under = En, LowVoltProg = Dis,
' Enhanced CPU = Dis, ALL FOLLOWING set to Not Protected.
'''''''''''''''''''''''''' ex Richard ''''''''''''''''''''''''''''''

#CONFIG

; Oscillator Selection bits
CONFIG OSC = INTIO7 ;Internal oscillator block, CLKOUT function on RA6, port function on RA7
; CONFIG OSC = INTIO67 ;Internal oscillator block, port function on RA6 and RA7
; CONFIG OSC = RCIO6 ;External RC oscillator, port function on RA6
; CONFIG OSC = HSPLL ;HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
; CONFIG OSC = ECIO6 ;EC oscillator, port function on RA6
; CONFIG OSC = EC ;EC oscillator, CLKOUT function on RA6
; CONFIG OSC = RC ;External RC oscillator, CLKO function on RA6
; CONFIG OSC = HS ;HS oscillator
; CONFIG OSC = XT ;XT oscillator
; CONFIG OSC = LP ;LP oscillator
;
; Fail-Safe Clock Monitor Enable bit
; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled
;
; Internal/External Oscillator Switchover bit
; CONFIG IESO = ON ;Oscillator Switchover mode enabled
CONFIG IESO = OFF ;Oscillator Switchover mode disabled
;
; Power-up Timer Enable bit
CONFIG PWRT = OFF ;PWRT disabled
; CONFIG PWRT = ON ;PWRT enabled
;
; Brown-out Reset Enable bits
CONFIG BOREN = SBORDIS ;Brown-out Reset enabled in hardware only (SBOREN is disabled)
; CONFIG BOREN = NOSLP ;Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; CONFIG BOREN = ON ;Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; CONFIG BOREN = OFF ;Brown-out Reset disabled in hardware and software
;
; Brown Out Reset Voltage bits
CONFIG BORV = 3 ;Minimum setting
; CONFIG BORV = 2 ;
; CONFIG BORV = 1 ;
; CONFIG BORV = 0 ;Maximum setting
;
; Watchdog Timer Enable bit
CONFIG WDT = ON ;WDT enabled
; CONFIG WDT = OFF ;WDT disabled (control is placed on the SWDTEN bit)
;
; Watchdog Timer Postscale Select bits
; CONFIG WDTPS = 32768 ;1:32768
; CONFIG WDTPS = 16384 ;1:16384
; CONFIG WDTPS = 8192 ;1:8192
; CONFIG WDTPS = 4096 ;1:4096
; CONFIG WDTPS = 2048 ;1:2048
; CONFIG WDTPS = 1024 ;1:1024
CONFIG WDTPS = 512 ;1:512
; CONFIG WDTPS = 256 ;1:256
; CONFIG WDTPS = 128 ;1:128
; CONFIG WDTPS = 64 ;1:64
; CONFIG WDTPS = 32 ;1:32
; CONFIG WDTPS = 16 ;1:16
; CONFIG WDTPS = 8 ;1:8
; CONFIG WDTPS = 4 ;1:4
; CONFIG WDTPS = 2 ;1:2
; CONFIG WDTPS = 1 ;1:1
;
; CCP2 MUX bit
CONFIG CCP2MX = PORTC ;CCP2 input/output is multiplexed with RC1
; CONFIG CCP2MX = PORTBE ;CCP2 input/output is multiplexed with RB3
;
; PORTB A/D Enable bit
; CONFIG PBADEN = ON ;PORTB<4:0> pins are configured as analog input channels on Reset
CONFIG PBADEN = OFF ;PORTB<4:0> pins are configured as digital I/O on Reset
;
; Low-Power Timer1 Oscillator Enable bit
; CONFIG LPT1OSC = ON ;Timer1 configured for low-power operation
CONFIG LPT1OSC = OFF ;Timer1 configured for higher power operation
;
; MCLR Pin Enable bit
CONFIG MCLRE = ON ;MCLR pin enabled; RE3 input pin disabled
; CONFIG MCLRE = OFF ;RE3 input pin enabled; MCLR disabled
;
; Stack Full/Underflow Reset Enable bit
CONFIG STVREN = ON ;Stack full/underflow will cause Reset
; CONFIG STVREN = OFF ;Stack full/underflow will not cause Reset
;
; Single-Supply ICSP Enable bit
; CONFIG LVP = ON ;Single-Supply ICSP enabled
CONFIG LVP = OFF ;Single-Supply ICSP disabled
;
; Extended Instruction Set Enable bit
; CONFIG XINST = ON ;Instruction set extension and Indexed Addressing mode enabled
CONFIG XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
;
; Background Debugger Enable bit
CONFIG DEBUG = OFF ;Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
; CONFIG DEBUG = ON ;Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
;
; Code Protection bit
CONFIG CP0 = OFF ;Block 0 (000800-003FFFh) not code-protected
; CONFIG CP0 = ON ;Block 0 (000800-003FFFh) code-protected
;
; Code Protection bit
CONFIG CP1 = OFF ;Block 1 (004000-007FFFh) not code-protected
; CONFIG CP1 = ON ;Block 1 (004000-007FFFh) code-protected
;
; Code Protection bit
CONFIG CP2 = OFF ;Block 2 (008000-00BFFFh) not code-protected
; CONFIG CP2 = ON ;Block 2 (008000-00BFFFh) code-protected
;
; Code Protection bit
CONFIG CP3 = OFF ;Block 3 (00C000-00FFFFh) not code-protected
; CONFIG CP3 = ON ;Block 3 (00C000-00FFFFh) code-protected
;
; Boot Block Code Protection bit
CONFIG CPB = OFF ;Boot block (000000-0007FFh) not code-protected
; CONFIG CPB = ON ;Boot block (000000-0007FFh) code-protected
;
; Data EEPROM Code Protection bit
CONFIG CPD = OFF ;Data EEPROM not code-protected
; CONFIG CPD = ON ;Data EEPROM code-protected
;
; Write Protection bit
CONFIG WRT0 = OFF ;Block 0 (000800-003FFFh) not write-protected
; CONFIG WRT0 = ON ;Block 0 (000800-003FFFh) write-protected
;
; Write Protection bit
CONFIG WRT1 = OFF ;Block 1 (004000-007FFFh) not write-protected
; CONFIG WRT1 = ON ;Block 1 (004000-007FFFh) write-protected
;
; Write Protection bit
CONFIG WRT2 = OFF ;Block 2 (008000-00BFFFh) not write-protected
; CONFIG WRT2 = ON ;Block 2 (008000-00BFFFh) write-protected
;
; Write Protection bit
CONFIG WRT3 = OFF ;Block 3 (00C000-00FFFFh) not write-protected
; CONFIG WRT3 = ON ;Block 3 (00C000-00FFFFh) write-protected
;
; Configuration Register Write Protection bit
CONFIG WRTC = OFF ;Configuration registers (300000-3000FFh) not write-protected
; CONFIG WRTC = ON ;Configuration registers (300000-3000FFh) write-protected
;
; Boot Block Write Protection bit
CONFIG WRTB = OFF ;Boot Block (000000-0007FFh) not write-protected
; CONFIG WRTB = ON ;Boot Block (000000-0007FFh) write-protected
;
; Data EEPROM Write Protection bit
CONFIG WRTD = OFF ;Data EEPROM not write-protected
; CONFIG WRTD = ON ;Data EEPROM write-protected
;
; Table Read Protection bit
CONFIG EBTR0 = OFF ;Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR0 = ON ;Block 0 (000800-003FFFh) protected from table reads executed in other blocks
;
; Table Read Protection bit
CONFIG EBTR1 = OFF ;Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR1 = ON ;Block 1 (004000-007FFFh) protected from table reads executed in other blocks
;
; Table Read Protection bit
CONFIG EBTR2 = OFF ;Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
; CONFIG EBTR2 = ON ;Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
;
; Table Read Protection bit
CONFIG EBTR3 = OFF ;Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
; CONFIG EBTR3 = ON ;Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
;
; Boot Block Table Read Protection bit
CONFIG EBTRB = OFF ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
; CONFIG EBTRB = ON ;Boot Block (000000-0007FFh) protected from table reads executed in other blocks
;
#ENDCONFIG

''''''''''''''''''''''''''''''''' end ex Richard ''''''''''''''''''''''''''''

'********************** DATA and DEFINES ***************************
DEFINE OSC 8
'Select INTIO1 (ClkOut) in the configuration menu at programming.
'Use OSCCON to select frequency & select internal oscillator block
'Use CRO to see if any ClkOut visible on Osc2/ClkOut pin 14(40) or 31(44)

Initialise:

LED1 var PORTE.1 'LATE.1 does not work either
LED2 var PORTE.2 'LATE.2 does not work either

TRISE = %00001000 'make sure PSP is OFF & MCLR active
PORTE = %00001000 '

' OSCCON = %11111110 ' 8 MHz Internal Osc Block
' ' 0------- IDLEN 0 = enters SLEEP on Sleep command = 4 uA
' ' 1------- IDLEN 1 = enters IDLE on Sleep command and draws 550 uA
' ' -111---- IRCF <2:0> Int Osc freq select 111 = 8 MHz
' ' -110---- IRCF <2:0> Int Osc freq select 110 = 4 MHz
' ' -101---- 2 MHz
' ' -100---- 1 MHz
' ' -011---- 500 kHz
' ' -010---- 250 kHz
' ' -010---- 125 kHz
' ' -000---- 31 kHz
' ' ----0--- OSTS Osc Startup Status - read only - ignore
' ' -----0-- IOFS IntOsc Freq Stable - read only - ignore
' ' ------00 System Clock Select 00 = Primary Osc
' ' ------01 Secondary (Timer1) oscillator
' ' ------1x Internal oscillator block

' WDTCON = %00000001 ' enables SWDT - needs WDT OFF in config
' ' xxxxxxx1 SWDTEN software controlled WDT enabled
ADCON0 = %00000000 ' ADC OFF
' xx0000-- CH<3:0> select analog channels
' ------0- 1 = Go, 0 = Done
' -------0 1 = ADC ON, 0 = ADC OFF
ADCON1 = %00001111 'VRef = Vdd, Vss, All ports digital
' configures all digital
' 00------ Unimplemented
' --00---- VCFG<1:0> Select Vcc & Gnd as ADC references
' ----1111 PCFG<3:0> A/D Port configuration see "register 19-1"
' ADCON2 = %00111111 'Left just (=8 bit), ADacq time = 20 Tad, ADClk = Frc
' 0------- ADFM 0 = Left Justified 8 bit mode
' -x111--- ACQ<2:0> A/D aquisition time = 20 Tad
' -----111 ADCS<2:0> A/D conversion clock select = Fr/c
CMCON = %00000111 ' Comparators OFF
' 00------ No comparator outputs
' --00---- No inversion on outputs
' ----0--- Vin to pins AN0 & AN1
' -----111 Comparators OFF
MainLoop:
High LED1 '
high led2

Pause 250 '

Low LED1 '
low led2

Pause 250 '

Goto mainloop '

ENDCODE

Any more suggestions or comments?
Thanks
BrianT