So I notice that some 18F chips have the old style configs like CONFIG1H, as well as the new style listed in their chipx.inc file. But other chips, like the 18F26J50 only have the new style, with no CONFIG1H style in the Microchip .inc file for that chip.
I have read the configs have been depreciated posts, where Darrel says ignore the warnings, they are just that ... warnings. However, with newer chips like the PIC18F26J50, is there a way to get around the error:
Error[176]c:\picbasic\26j50-~.asm 101 :CONFIG Directive Error: (setting "48" not found for the processor 18F26J50) ? It seems so close, to only be held up by defining the oscillator!
I get the above error when I try to use :
Code:
DEFINE OSC 48
ASM
CONFIG OSC=HSPLL
CONFIG CPUDIV=OSC1
CONFIG PLLDIV=5
CONFIG LPT1OSC=OFF
CONFIG CP0=OFF
CONFIG WDTEN=ON
CONFIG XINST=OFF
CONFIG IOL1WAY=OFF
CONFIG STVREN=OFF
CONFIG T1DIG=ON
CONFIG FCMEN=OFF
CONFIG WDTPS=512
CONFIG RTCOSC=T1OSCREF
ENDASM
If I comment out the DEFINE OSC 48, all appears good. If I try to define the OSC setting, I get the 176 error.
..there are no CONFIG1H's here...
Code:
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Watchdog Timer:
; WDTEN = OFF Disabled - Controlled by SWDTEN bit
; WDTEN = ON Enabled
;
; PLL Prescaler Selection bits:
; PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
; PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
; PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
; PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
; PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
; PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
; PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
;
; Stack Overflow/Underflow Reset :
; STVREN = OFF Disabled
; STVREN = ON Enabled
;
; Extended Instruction Set:
; XINST = OFF Disabled
; XINST = ON Enabled
;
; CPU System Clock Postscaler:
; CPUDIV = OSC4_PLL6 CPU system clock divide by 6
; CPUDIV = OSC3_PLL3 CPU system clock divide by 3
; CPUDIV = OSC2_PLL2 CPU system clock divide by 2
; CPUDIV = OSC1 No CPU system clock divide
;
; Code Protect:
; CP0 = ON Program memory is code-protected
; CP0 = OFF Program memory is not code-protected
;
; Oscillator:
; OSC = INTOSC INTOSC
; OSC = INTOSCO INTOSCO (CLKO-RA6)
; OSC = INTOSCPLL INTOSCPLL
; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6)
; OSC = HS HS, USB-HS
; OSC = HSPLL HS+PLL, USB-HS+PLL
; OSC = EC EC (CLKO-RA6), USB-EC
; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL
;
; T1OSCEN Enforcement:
; T1DIG = OFF Secondary Oscillator clock source may not be selected
; T1DIG = ON Secondary Oscillator clock source may be selected
;
; Low-Power Timer1 Oscillator:
; LPT1OSC = ON Low-power operation
; LPT1OSC = OFF High-power operation
;
; Fail-Safe Clock Monitor:
; FCMEN = OFF Disabled
; FCMEN = ON Enabled
;
; Internal External Oscillator Switch Over Mode:
; IESO = OFF Disabled
; IESO = ON Enabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; DSWDT Clock Select:
; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI
; DSWDTOSC = INTOSCREF DSWDT uses INTRC
;
; RTCC Clock Select:
; RTCOSC = INTOSCREF RTCC uses INTRC
; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI
;
; Deep Sleep BOR:
; DSBOREN = OFF Disabled
; DSBOREN = ON Enabled
;
; Deep Sleep Watchdog Timer:
; DSWDTEN = OFF Disabled
; DSWDTEN = ON Enabled
;
; Deep Sleep Watchdog Postscaler:
; DSWDTPS = 2 1:2 (2.1 ms)
; DSWDTPS = 8 1:8 (8.3 ms)
; DSWDTPS = 32 1:32 (33 ms)
; DSWDTPS = 128 1:128 (132 ms)
; DSWDTPS = 512 1:512 (528 ms)
; DSWDTPS = 2048 1:2,048 (2.1 seconds)
; DSWDTPS = 8192 1:8,192 (8.5 seconds)
; DSWDTPS = K32 1:32,768 (34 seconds)
; DSWDTPS = K131 1:131,072 (135 seconds)
; DSWDTPS = K524 1:524,288 (9 minutes)
; DSWDTPS = M2 1:2,097,152 (36 minutes)
; DSWDTPS = M8 1:8,388,608 (2.4 hours)
; DSWDTPS = M33 1:33,554,432 (9.6 hours)
; DSWDTPS = M134 1:134,217,728 (38.5 hours)
; DSWDTPS = M536 1:536,870,912 (6.4 days)
; DSWDTPS = G2 1:2,147,483,648 (25.7 days)
;
; IOLOCK One-Way Set Enable bit:
; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed
; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once
;
; MSSP address masking:
; MSSP7B_EN = MSK5 5 Bit address masking mode
; MSSP7B_EN = MSK7 7 Bit address masking mode
;
; Write/Erase Protect Page Start/End Location:
; WPFP = PAGE_0 Write Protect Program Flash Page 0
; WPFP = PAGE_1 Write Protect Program Flash Page 1
; WPFP = PAGE_2 Write Protect Program Flash Page 2
; WPFP = PAGE_3 Write Protect Program Flash Page 3
; WPFP = PAGE_4 Write Protect Program Flash Page 4
; WPFP = PAGE_5 Write Protect Program Flash Page 5
; WPFP = PAGE_6 Write Protect Program Flash Page 6
; WPFP = PAGE_7 Write Protect Program Flash Page 7
; WPFP = PAGE_8 Write Protect Program Flash Page 8
; WPFP = PAGE_9 Write Protect Program Flash Page 9
; WPFP = PAGE_10 Write Protect Program Flash Page 10
; WPFP = PAGE_11 Write Protect Program Flash Page 11
; WPFP = PAGE_12 Write Protect Program Flash Page 12
; WPFP = PAGE_13 Write Protect Program Flash Page 13
; WPFP = PAGE_14 Write Protect Program Flash Page 14
; WPFP = PAGE_15 Write Protect Program Flash Page 15
; WPFP = PAGE_16 Write Protect Program Flash Page 16
; WPFP = PAGE_17 Write Protect Program Flash Page 17
; WPFP = PAGE_18 Write Protect Program Flash Page 18
; WPFP = PAGE_19 Write Protect Program Flash Page 19
; WPFP = PAGE_20 Write Protect Program Flash Page 20
; WPFP = PAGE_21 Write Protect Program Flash Page 21
; WPFP = PAGE_22 Write Protect Program Flash Page 22
; WPFP = PAGE_23 Write Protect Program Flash Page 23
; WPFP = PAGE_24 Write Protect Program Flash Page 24
; WPFP = PAGE_25 Write Protect Program Flash Page 25
; WPFP = PAGE_26 Write Protect Program Flash Page 26
; WPFP = PAGE_27 Write Protect Program Flash Page 27
; WPFP = PAGE_28 Write Protect Program Flash Page 28
; WPFP = PAGE_29 Write Protect Program Flash Page 29
; WPFP = PAGE_30 Write Protect Program Flash Page 30
; WPFP = PAGE_31 Write Protect Program Flash Page 31
; WPFP = PAGE_32 Write Protect Program Flash Page 32
; WPFP = PAGE_33 Write Protect Program Flash Page 33
; WPFP = PAGE_34 Write Protect Program Flash Page 34
; WPFP = PAGE_35 Write Protect Program Flash Page 35
; WPFP = PAGE_36 Write Protect Program Flash Page 36
; WPFP = PAGE_37 Write Protect Program Flash Page 37
; WPFP = PAGE_38 Write Protect Program Flash Page 38
; WPFP = PAGE_39 Write Protect Program Flash Page 39
; WPFP = PAGE_40 Write Protect Program Flash Page 40
; WPFP = PAGE_41 Write Protect Program Flash Page 41
; WPFP = PAGE_42 Write Protect Program Flash Page 42
; WPFP = PAGE_43 Write Protect Program Flash Page 43
; WPFP = PAGE_44 Write Protect Program Flash Page 44
; WPFP = PAGE_45 Write Protect Program Flash Page 45
; WPFP = PAGE_46 Write Protect Program Flash Page 46
; WPFP = PAGE_47 Write Protect Program Flash Page 47
; WPFP = PAGE_48 Write Protect Program Flash Page 48
; WPFP = PAGE_49 Write Protect Program Flash Page 49
; WPFP = PAGE_50 Write Protect Program Flash Page 50
; WPFP = PAGE_51 Write Protect Program Flash Page 51
; WPFP = PAGE_52 Write Protect Program Flash Page 52
; WPFP = PAGE_53 Write Protect Program Flash Page 53
; WPFP = PAGE_54 Write Protect Program Flash Page 54
; WPFP = PAGE_55 Write Protect Program Flash Page 55
; WPFP = PAGE_56 Write Protect Program Flash Page 56
; WPFP = PAGE_57 Write Protect Program Flash Page 57
; WPFP = PAGE_58 Write Protect Program Flash Page 58
; WPFP = PAGE_59 Write Protect Program Flash Page 59
; WPFP = PAGE_60 Write Protect Program Flash Page 60
; WPFP = PAGE_61 Write Protect Program Flash Page 61
; WPFP = PAGE_62 Write Protect Program Flash Page 62
; WPFP = PAGE_63 Write Protect Program Flash Page 63
;
; Write/Erase Protect Region Select bit (valid when WPDIS = 0):
; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected
; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected
;
; Write/Erase Protect Configuration Region :
; WPCFG = ON Configuration Words page erase/write-protected
; WPCFG = OFF Configuration Words page not erase/write-protected
;
; Write Protect Disable bit:
; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled
; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored
;
;==========================================================================
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
Is the only solution is to edit all configs in the PBP include file, or am I missing something. If this has already been covered, let me have it....
I notice that the 18F4550 has both styles in it's include file, like this:
Code:
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; PLL Prescaler Selection bits:
; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
; PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
; PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
; PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
; PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
; PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
; PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
; PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
;
; CPU System Clock Postscaler:
; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
;
; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale
; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2
;
; Oscillator Selection bits:
; FOSC = XT_XT XT oscillator, XT used by USB
; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
; FOSC = INTOSC_XT Internal oscillator, XT used by USB
; FOSC = INTOSC_HS Internal oscillator, HS used by USB
; FOSC = HS HS oscillator, HS used by USB
; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF Oscillator Switchover mode disabled
; IESO = ON Oscillator Switchover mode enabled
;
; Power-up Timer Enable bit:
; PWRT = ON PWRT enabled
; PWRT = OFF PWRT disabled
;
; Brown-out Reset Enable bits:
; BOR = OFF Brown-out Reset disabled in hardware and software
; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
; Brown-out Voltage bits:
; BORV = 0 Maximum setting
; BORV = 1
; BORV = 2
; BORV = 3 Minimum setting
;
; USB Voltage Regulator Enable bit:
; VREGEN = OFF USB voltage regulator disabled
; VREGEN = ON USB voltage regulator enabled
;
; Watchdog Timer Enable bit:
; WDT = OFF HW Disabled - SW Controlled
; WDT = ON HW Enabled - SW Disabled
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; MCLR Pin Enable bit:
; MCLRE = OFF RE3 input pin enabled; MCLR disabled
; MCLRE = ON MCLR pin enabled; RE3 input pin disabled
;
; Low-Power Timer 1 Oscillator Enable bit:
; LPT1OSC = OFF Timer1 configured for higher power operation
; LPT1OSC = ON Timer1 configured for low-power operation
;
; PORTB A/D Enable bit:
; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset
;
; CCP2 MUX bit:
; CCP2MX = OFF CCP2 input/output is multiplexed with RB3
; CCP2MX = ON CCP2 input/output is multiplexed with RC1
;
; Stack Full/Underflow Reset Enable bit:
; STVREN = OFF Stack full/underflow will not cause Reset
; STVREN = ON Stack full/underflow will cause Reset
;
; Single-Supply ICSP Enable bit:
; LVP = OFF Single-Supply ICSP disabled
; LVP = ON Single-Supply ICSP enabled
;
; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
; ICPRT = OFF ICPORT disabled
; ICPRT = ON ICPORT enabled
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
; Code Protection bit Block 0:
; CP0 = ON Block 0 (000800-001FFFh) code-protected
; CP0 = OFF Block 0 (000800-001FFFh) not code-protected
;
; Code Protection bit Block 1:
; CP1 = ON Block 1 (002000-003FFFh) code-protected
; CP1 = OFF Block 1 (002000-003FFFh) not code-protected
;
; Code Protection bit Block 2:
; CP2 = ON Block 2 (004000-005FFFh) code-protected
; CP2 = OFF Block 2 (004000-005FFFh) not code-protected
;
; Code Protection bit Block 3:
; CP3 = ON Block 3 (006000-007FFFh) code-protected
; CP3 = OFF Block 3 (006000-007FFFh) not code-protected
;
; Boot Block Code Protection bit:
; CPB = ON Boot block (000000-0007FFh) code-protected
; CPB = OFF Boot block (000000-0007FFh) not code-protected
;
; Data EEPROM Code Protection bit:
; CPD = ON Data EEPROM code-protected
; CPD = OFF Data EEPROM not code-protected
;
; Write Protection bit Block 0:
; WRT0 = ON Block 0 (000800-001FFFh) write-protected
; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected
;
; Write Protection bit Block 1:
; WRT1 = ON Block 1 (002000-003FFFh) write-protected
; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected
;
; Write Protection bit Block 2:
; WRT2 = ON Block 2 (004000-005FFFh) write-protected
; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected
;
; Write Protection bit Block 3:
; WRT3 = ON Block 3 (006000-007FFFh) write-protected
; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected
;
; Boot Block Write Protection bit:
; WRTB = ON Boot block (000000-0007FFh) write-protected
; WRTB = OFF Boot block (000000-0007FFh) not write-protected
;
; Configuration Register Write Protection bit:
; WRTC = ON Configuration registers (300000-3000FFh) write-protected
; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
;
; Data EEPROM Write Protection bit:
; WRTD = ON Data EEPROM write-protected
; WRTD = OFF Data EEPROM not write-protected
;
; Table Read Protection bit Block 0:
; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 1:
; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 2:
; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 3:
; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
;
; Boot Block Table Read Protection:
; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks
; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1L 300000h
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1L EQU H'300000'
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1L Options --------------------------------------------------
_PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly)
_PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input)
_PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input)
_PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input)
_PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input)
_PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input)
_PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input)
_PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input)
_CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
_CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
_CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
_CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
_USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale
_USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2
;----- CONFIG1H Options --------------------------------------------------
_FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB
_FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB
_FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB
_FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB
_FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB
_FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB
_FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB
_FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB
_FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB
_FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB
_FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB
_FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_0_2L EQU H'E7' ; Maximum setting
_BORV_1_2L EQU H'EF' ;
_BORV_2_2L EQU H'F7' ;
_BORV_3_2L EQU H'FF' ; Minimum setting
_VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled
_VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled
_WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation
_PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset
_PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset
_CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3
_CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
_ICPRT_OFF_4L EQU H'DF' ; ICPORT disabled
_ICPRT_ON_4L EQU H'FF' ; ICPORT enabled
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected
_CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected
_CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected
_CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected
_CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected
_CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected
_CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected
_CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected
_CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected
_CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected
_CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected
_WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected
_WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected
_WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected
_WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected
_WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected
_WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected
_WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected
_WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected
_WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected
_WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected
_WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
_EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
_EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
_EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
_EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
_EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
_EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks
_EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks
_EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Thanks,
Walter
Help in setting internal clock on 18F1220 device
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Originally Posted by wbubel
... wrong.
.
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