Plldiv...

[Armando Herjim]

Hello everybody... I am trying to make some USB communication and there´s something I´d like to know.... I use these lines on my 18F4550.INC file: (this post is more about the configuration in this file than usb communication)

CONFIG FOSC = HS ;I am using a 12 MHz xtal, do I need the HSPLL_HS
;option for the usb communication?
CONFIG USBDIV = 2 ; USB clock source comes from the 96MHz PLL
CONFIG PLLDIV = 3 ; If usbdiv = 2 and my xtal is 12 MHz then is this line requiered? if not, what does this line do exactly?

if usbdiv = 2 then the usb clock source will be the pll always no matter what the fosc configuration is??

Thanks to all!

Best Regards.

Armando Herjim.

P.D. Is the word "requiered" well written?

[mister_e]

mmmpffmmppffm i'll try to explain this one.

The PLLDIV factor is the one you need to reduce the external OSC to 4MHZ. Yes the internal OSC will always work @4MHZ and raise it to 96MHZ... later

In your cas 12MHZ external /4MHZ internal = PLLDIV should be 3.. you have it good

USBDIV/2 will be the PIC OSC SPEED. in this case 48MHZ.

P.D. Is the word "requiered" well written?

i could be wrong... but i think it's 'required' or 'needed'

Francais un jour, francais toujours