DT Ints not working on 16F18426

[wjsmarine]

Hi All,

First time using subject PIC and have it running well with all other tasks except no recognition of a button push via IOC.

The relevant section is below, taken from the main code (11k words) to avoid confusion. I've RTFM a number of times
but can't seem to get anywhere. All suggestions welcome.

Cheers,
Bill

'****************************************************************
'*  Name    : Test_IOCAN.pbp                                    *
'*  Author  : WJS                                               *
'*  Date    : 27/08/2023                                        *
'*  Device  : 16F18426                                          *
'*  Version : 1.0, PBP 3.1.5.4                                  *
'*  Notes   : Test interrupt code for pushbutton on A.2 pulled  *
'*          : up 10k.                                           *
'****************************************************************

' Compiles and runs but no sign of Int. 

 
#CONFIG ; 16F18426
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_SBOREN & _BORV_LO & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_ON
    __config _CONFIG3, _WDTCPS_WDTCPS_31 & _WDTE_SWDTEN & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _BBSIZE_BB512 & _BBEN_OFF & _SAFEN_OFF & _WRTAPP_OFF & _WRTB_OFF & _WRTC_OFF & _WRTD_OFF & _WRTSAF_OFF & _LVP_OFF
    __config _CONFIG5, _CP_OFF
#ENDCONFIG

' -----[ Initialization 16F18426]--------------------------------------------------------------------------------------- 

    DEFINE  OSC 32              ' Adjust to suit design.

    IOCAF = 0                   ' Clear the Int flag.
    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.
    PIE0 = %00010001            ' Enable IOCIE, INTE bits.
    IOCAP = 0                   ' Disable IOC rising edge A.
    IOCAN = %00000100           ' Enable IOC falling edge A2.

    ADCON0 = 0                  ' No ADC.
    ANSELA = %00000000          ' All Dig.
    ANSELC = %00000000          ' All Dig.

    CM1CON0 = 0                 ' Comparators off.
    FVRCON = %0                 ' Disabled.

    TRISA = %000100             ' A.2 pulled up, pushbutton to ground.
    TRISC = %000000             ' C.5 serout to PC via 1k, C.4 led to ground via 1k.

LED     var PORTC.4             ' Led via 1k to ground.
To_PC   var PORTC.5             ' Serout to PC at 9600, Inv. Idles low, data goes high.      
serI96  con 16468               ' 9600 Baud Inverted.

    Include "MODEDEFS.BAS"      ' Include Shiftin/out modes.
    INCLUDE "DT_INTS-14.bas"    ' 
    INCLUDE "ReEnterPBP.bas"    ; Include if using PBP interrupts.	

ASM
INT_LIST  macro    ; IntSrce,  Label,  Type,  ResetFlag?
        INT_Handler    IOC_INT,  _PB,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

  serout2 to_PC,seri96,[10,13,"I'm Alive!",10,13] ' Confirm.

Begin:
    LED = 1     ' On.
    pause 500   ' 2hz.
    LED = 0     ' Off.
    pause 500   ' 2hz.
    goto begin  ' Cycle.


'---[IOC - interrupt handler]---------------------------------------------------
PB: ' Pushbutton to get here.
 if IOCAF.2 = 1 then        ' Bit 1 (A.2) set.
  serout2 to_PC,seri96,[10,13,"Int!",10,13] ' Testing.
 endif 

  IOCAF = 0                 ' Clear the Int flag.
@ INT_RETURN
  

end

[tumbleweed]

If you're using the stock DT_INTS-14.bas (v1.10), it's not going to work with the 16F18426.
The interrupt register bits are completely different.

[HenrikOlsson]

I think you also need to enable the interrupt

@ INT_ENABLE IOC_INT

[wjsmarine]

Thanks Henrik,

I must have had a brain fart leaving that out... but its inclusion made no difference.

@ tumbleweed
I'm thinking you've nailed it - can you offer any suggestions to correct the situation? I'd like to learn from this as it will reappear, no doubt, with various other new chips.

Cheers,
Bill

[richard]

DT_INTS-14.bas (v1.10)
SNIPPET


#define ALL_INT INTCON,GIE, INTCON,GIE ;-- Global Interrupts *
#define AT1_INT PIR5,AT1IF, PIE5,AT1IE ;--ANGULAR TIMER
#define T1GATE_INT PIR1,TMR1GIF, PIE1,TMR1GIE ;-- Timer1 Gate *
#define INT_INT INTCON,INTF, INTCON,INTE ;-- External INT
#define GPC_INT INTCON,GPIF, INTCON,GPIE ;-- GPIO Int On Change *
#define IOC_INT INTCON,IOCIF, INTCON,IOCIE ;-- Int On Change *
#define RAC_INT INTCON,RAIF, INTCON,RAIE ;-- RA Port Change *
#define RBC_INT INTCON,RBIF, INTCON,RBIE ;-- RB Port Change
#define RABC_INT INTCON,RABIF, INTCON,RABIE ;-- RAB Port Change *
#define ECIOC_INT PIR0,IOCIF, PIE0,IOCIE ;-- ENHANCED CORE_Int On Change *

ADD THIS THEN YOU HAVE A NEW TYPE OF INTERRUPT ECIOC_INT FOR THOSE OR SIMILAR chips

[tumbleweed]

You need to redo the section that #defines the interrupt bit locations.
It's in the section that looks like this...

  #define INT_INT      	PIR0,INTF,  PIE0,INTE       ;-- External INT
  #define IOC_INT      	PIR0,IOCIF, PIE0,IOCIE     ;-- Int On Change       *

You need to get the datasheet for the part and change the 'PIR0,INTF, PIE0,INTE' statements to match.

Somewhere along the line I got a file for the 16F18326... don't remember where or who did it.
Yours would be similar. I've attached it for ref, but I haven't checked or tested it.

[wjsmarine]

Thank you gentlemen, that did the trick.

I'll make notes ready for the next time a new chip gives issues.

Kind regards,
Bill

[wjsmarine]

Hi Folks,

I was too quick in replying all was good - it isn't. The test I performed was only to see the serial Int! and then left it for more urgent tasks.

When I went back to do more testing I found the LED frozen, although further button pushes still gave the Int! - so the running task never gets returned to.

Am I missing something obvious here or are further mods required?

I've attached the edited Inc file (thank you Richard, tumbleweed and Henrik).

Cheers,
Bill

'****************************************************************
'*  Name    : Test_IOCAN.pbp                                    *
'*  Author  : WJS                                               *
'*  Date    : 27/08/2023                                        *
'*  Device  : 16F18426                                          *
'*  Version : 1.0, PBP 3.1.5.4                                  *
'*  Notes   : Test interrupt code for pushbutton on A.2 pulled  *
'*          : up 10k.                                           *
'****************************************************************
'
' Uses modified DT_INTS-14.bas (v1.10) now renamed DT_INTS-14 v1-2.bas for 16F18426
' - Ints take place but does not appear to return to program.
'

#CONFIG ; 16F18426
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_SBOREN & _BORV_LO & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_ON
    __config _CONFIG3, _WDTCPS_WDTCPS_31 & _WDTE_SWDTEN & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _BBSIZE_BB512 & _BBEN_OFF & _SAFEN_OFF & _WRTAPP_OFF & _WRTB_OFF & _WRTC_OFF & _WRTD_OFF & _WRTSAF_OFF & _LVP_OFF
    __config _CONFIG5, _CP_OFF
#ENDCONFIG

' -----[ Initialization 16F18426]--------------------------------------------------------------------------------------- 

    DEFINE  OSC 32              ' Adjust to suit design.
; PIR0,IOCIF, PIE0,IOCIE         ;-- ENHANCED CORE_Int On Change 

    IOCAF = 0                   ' Clear the Int flag.
    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.
    PIE0 = %00010001            ' Enable IOCIE, INTE bits.
    
    IOCAP = 0                   ' Disable IOC rising edge A.
    IOCAN = %00000100           ' Enable IOC falling edge A2.

    ADCON0 = 0                  ' No ADC.
    ANSELA = %00000000          ' All Dig.
    ANSELC = %00000000          ' All Dig.

    CM1CON0 = 0                 ' Comparators off.
    FVRCON = %0                 ' Disabled.

    TRISA = %000100             ' A.2 pulled up, pushbutton to ground.
    TRISC = %000000             ' C.5 serout to PC via 1k, C.4 led to ground via 1k.

LED     var PORTC.4             ' Led via 1k to ground.
To_PC   var PORTC.5             ' Serout to PC at 9600, Inv. Idles low, data goes high.      
serI96  con 16468               ' 9600 Baud Inverted.

    Include "MODEDEFS.BAS"      ' Include Shiftin/out modes.
    INCLUDE "DT_INTS-14 v1-2.bas"   ' New version for Enhanced chips.
    INCLUDE "ReEnterPBP.bas"        ; Include if using PBP interrupts.	

ASM
INT_LIST  macro        ; IntSrce, Label, Type,  ResetFlag?
        INT_Handler    ECIOC_INT,  _PB,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

@ INT_ENABLE ECIOC_INT       ; Enable the Int.

  serout2 to_PC,seri96,[10,13,"I'm Alive!",10,13] ' Confirm.

Begin:
    LED = 1     ' On.
    pause 500   ' 2hz.
    LED = 0     ' Off.
    pause 500   ' 2hz.
    goto begin  ' Cycle.


'---[IOC - interrupt handler]---------------------------------------------------
PB: ' Pushbutton to get here.
 if IOCAF.2 = 1 then        ' Bit 1 (A.2) set.
  serout2 to_PC,seri96,[10,13,"Int!",10,13] ' Testing.
 endif 

  IOCAF = 0                 ' Clear the Int flag.

@ INT_RETURN
  

end

[richard]

The closest match i have to that chip is 16f18875 and i can confirm it does not work
for ioc int with modified file. the chip works fine using that ioc ints with asm code
totally unsure why dt ints fails at this point

'****************************************************************'*  Name    : Test_IOCAN.pbp                                    *
'*  Author  :                                               *
'*  Date    :                                         *
'*  Device  : 16F18875                                         *
'*  Version : 1.0, PBP 3.1.5.4                                  *
'*  Notes   : Test interrupt code for pushbutton on A.2 pulled  *
'*          : up 10k.                                           *
'****************************************************************




  #CONFIG
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
    __config _CONFIG5, _CP_OFF & _CPD_OFF
  #ENDCONFIG


' -----[ Initialization 16F18875]--------------------------------------------------------------------------------------- 


    DEFINE  OSC 32              ' Adjust to suit design.


    IOCAF = 0                   ' Clear the Int flag.
    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.
    PIE0 = %00010001            ' Enable IOCIE, INTE bits.
    IOCAP = 0                   ' Disable IOC rising edge A.
    IOCAN = %00000100           ' Enable IOC falling edge A2.


    
    ANSELA = %00000000          ' All Dig.
    ANSELC = %00000000          ' All Dig.


    TRISA = %000100             ' A.2 pulled up, pushbutton to ground.
    TRISC = %000000             ' C.5 serout to PC via 1k, C.4 led to ground via 1k.
    DEFINE DEBUG_REG PORTC
    DEFINE DEBUG_BIT 5
    DEFINE DEBUG_BAUD 9600
    DEFINE DEBUG_MODE 0
    LATC.5 = 1
    LED     var PORTC.4             ' Led via 1k to ground.
    DEFINE INTHAND PB
    DEBUG       "I'm Alive!",13
    Switch var bYTE      $7f  SYSTEM 
    switch = 0    
   
   
Begin:
    LED = 1     ' On.
    if switch=1 then 
        switch=0 
        DEBUG       "Int!",13
    endif 
    pause 500   ' 2hz.
    LED = 0     ' Off.
    if switch=1 then 
        switch=0 
        DEBUG       "Int!",13
    endif   
    pause 500   ' 2hz.
goto begin  ' Cycle.






ASM
PB
 banksel IOCAF
 btfsc IOCAF,2
 bsf Switch,0                      ; set bit0 in Switch to 1
 bcf IOCAF,2
 RETFIE
endasm
  


end

[tumbleweed]

I took a look at the asm code produced by post 8 and I don't see anything that jumps out as being wrong, so I don't know why it's having a problem.

One thing I would change... get rid of this

    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.

It's not a good idea to manipulate the enable bits until everything is setup.
DT_INTS enables GIE and PEIE right before it exits the INT_CREATE macro.

If you want to clear the INTEDG bit then just clear that one... INTCON.0 = 0

[tumbleweed]

Not sure how I missed this the first time around, but you're manually enabling both the IOC and INT interrupts.
Don't do that. Get rid of both these lines:

    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.
    PIE0 = %00010001            ' Enable IOCIE, INTE bits.

There is no handler defined for the INT interrupt, which is on the same pin as your IOC (pin RA2).
Once INT gets set there's nothing to clear it, so you never really exit the ISR... it immediately gets reinvoked when the RETFIE executes.

[wjsmarine]

Apologies for the late reply.

@tumbleweed
your mods got it working, many thanks for your advice.

@Richard
no joy using the ASM approach - the led locks up in the condition it was at the moment of button push and no Int! seen.
Removing INTCON and/or PIE0 (as with tumbleweed info) stops any interrupt happening so the led blinks away. If you want I can send
a couple of 16F18426 for you to test Richard. Let me know please.

Cheers,
Bill

[richard]

i still can't get it to work with dt ints the asm code worked perfectly, i have been using proteus to simulate it
i will gladly take up your offer and try it on the real thing, something is screwy with this i cannot get any dt-ints at all to work for that chip.
ps can you post the code that works. maybe i just forget how to use dt-ints i don't use pbp much these days

[Ioannis]

I am also interested in that chip series and would like to know if DT-INTS can finally work on these chips.

Thanks all for the effort,

Ioannis

[wjsmarine]

Hi Richard,

Okay, see below... The Inc file hasn't changed (attached previously).

If you "...i don't use pbp much these days" then I can't thank you enough for continuing to monitor and help us plebs. Sending you some samples is the least I can do.
I'll add a few other new chips in also in the hope they become supported at some stage ('other' compilers support them already...) plus a few others.

Cheers,
Bill

'****************************************************************
'*  Name    : Test_IOCAN.pbp                                    *
'*  Author  : WJS                                               *
'*  Date    : 27/08/2023                                        *
'*  Device  : 16F18426                                          *
'*  Version : 1.0, 391 words using PBP 3.1.5.4                  *
'*  Notes   : Test interrupt code for pushbutton on A.2 pulled  *
'*          : up 10k.                                           *
'****************************************************************
'
' Uses modified DT_INTS-14.bas (v1.10) now renamed DT_INTS-14 v1-2.bas for 16F18426
' - Ints take place but does not appear to return to program (fixed - see below).
'
' INTCON and PIE0 removed per tumbleweed's advice: 
' [www.picbasic.co.uk/forum/showthread.php/26635-DT-Ints-not-working-on-16F18426]
' now working correctly.  See also Test_IOCAN 2 using Richard's ASM (which doesn't work).
 
#CONFIG ; 16F18426
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTS_PWRT_64 & _LPBOREN_OFF & _BOREN_SBOREN & _BORV_LO & _ZCDDIS_OFF & _PPS1WAY_OFF & _STVREN_ON
    __config _CONFIG3, _WDTCPS_WDTCPS_31 & _WDTE_SWDTEN & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _BBSIZE_BB512 & _BBEN_OFF & _SAFEN_OFF & _WRTAPP_OFF & _WRTB_OFF & _WRTC_OFF & _WRTD_OFF & _WRTSAF_OFF & _LVP_OFF
    __config _CONFIG5, _CP_OFF
#ENDCONFIG

' -----[ Initialization 16F18426]--------------------------------------------------------------------------------------- 

    DEFINE  OSC 32              ' Adjust to suit design.

    IOCAF = 0                   ' Clear the Int flag.

;    INTCON = %11000000          ' Enable GIE, PEIE, falling edge.
;See: www.picbasic.co.uk/forum/showthread.php/26635-DT-Ints-not-working-on-16F18426?p=154517#post154517
;It's not a good idea to manipulate the enable bits until everything is setup.
;DT_INTS enables GIE and PEIE right before it exits the INT_CREATE macro.
;If you want to clear the INTEDG bit then just clear that one... INTCON.0 = 0    
    
;    PIE0 = %00010001            ' Enable IOCIE, INTE bits.
    
    IOCAP = 0                   ' Disable IOC rising edge A.
    IOCAN = %00000100           ' Enable IOC falling edge A2.

    ADCON0 = 0                  ' No ADC.
    ANSELA = %00000000          ' All Dig.
    ANSELC = %00000000          ' All Dig.

    CM1CON0 = 0                 ' Comparators off.
    FVRCON = %0                 ' Disabled.

    TRISA = %000100             ' A.2 pulled up, pushbutton to ground.
    TRISC = %000000             ' C.5 serout to PC via 1k, C.4 led to ground via 1k.

LED     var PORTC.4             ' Led via 1k to ground.
To_PC   var PORTC.5             ' Serout to PC at 9600, Inv. Idles low, data goes high.      
serI96  con 16468               ' 9600 Baud Inverted.

    Include "MODEDEFS.BAS"      ' Include Shiftin/out modes.
    INCLUDE "DT_INTS-14 v1-2.bas"   ' New version for Enhanced chips.
    INCLUDE "ReEnterPBP.bas"        ; Include if using PBP interrupts.	

ASM
INT_LIST  macro        ; IntSrce, Label, Type,  ResetFlag?
        INT_Handler    ECIOC_INT,  _PB,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

@ INT_ENABLE ECIOC_INT       ; Enable the Int.

  serout2 to_PC,seri96,[10,13,"I'm Alive!",10,13] ' Confirm.

Begin:
    LED = 1     ' On.
    pause 500   ' 2hz.
    LED = 0     ' Off.
    pause 500   ' 2hz.
    goto begin  ' Cycle.


'---[IOC - interrupt handler]---------------------------------------------------
PB: ' Pushbutton to get here.
 if IOCAF.2 = 1 then        ' Bit 1 (A.2) set.
  serout2 to_PC,seri96,[10,13,"Int!",10,13] ' Testing.
 endif 

  IOCAF = 0                 ' Clear the Int flag.

@ INT_RETURN
  

end

[tumbleweed]

Glad it's working. If you run across anything funny let us know.

There are a few bytes of ram reserved by DT_INTS for things that aren't needed, so they could be gotten rid of too but it's not hurting anything.

I'll add a few other new chips in also in the hope they become supported at some stage

As long as the chip is supported by mpasmx 5.87 then you've got a shot at it. That's basically any device that has an existing file in the DEVICES folder,
with the exception of the 18FxxQ84. That one is listed as supported by mpasmx but it doesn't work (that's an mpasmx fault, not pbp).

Anything past that and I don't think you'll see it get added... mpasmx is at the end of its life unless it's extended like the Swordfish folks have done for the 18F series.

I wouldn't trust proteus simulations to get it right, especially with these new chips.

[richard]

Bit the bullet and fished out an old 16f18875 from curiosity hpc board,
code works fine. seems proteus fails to emulate that chip properly
looks very much like the switch release triggers another interrupt that is not easily serviceable

[amgen]

One important thing I learned from my EET courses years ago ..... circuits have 2 responses to a change in voltage/current. There is an initial response that relates mostly to inductance and capacitance and previous state of circuit, then there is the 'steady state response' that comes after the circuit settles to constant state (micro/milli seconds later). That is not exactly referring to switch/contact bounce, but the interrupt could be triggered/cleared many times from contact bounce unless there is some kind of circuit that debounces the mechanical switch. One kind of test could be done is have the interrupt count/display how many times it gets triggered from a switch press.

[richard]

do simulated switches bounce in a simulated circuit simulation?
do androids dream of electric sheep ?
so many unknowns

[amgen]

do simulated switches bounce in a simulated circuit simulation?

I would suppose that there are good simulations and faulty simulations

[tumbleweed]

looks very much like the switch release triggers another interrupt that is not easily serviceable

That's one of the reasons why it's usually better NOT to use interrupts to handle things like button presses and just poll it.
In your main loop you can still use the IOC IF flag to check and see if you need to look for a key press, but there you can add debounce delays, etc... things that don't really belong in an ISR.

Polling for it in the main loop also gets around the problems created by getting interrupted in the middle of things, stuff like I2C, displays, serial ports, etc. that can't really get interrupted if they're used in both main and the ISR.

[Ioannis]

Tottaly agree with that.

I got in a rabbit hole trying to make a keyboard matrix work in an ISR along with debounce etc. Just a waste of time...

A tight loop is just fine. And as tumbleweed noted, use Interrupt just to note MCU that a key was pressed, maybe wake it up from sleep. Then a loop will do the rest.

Even if other interrupts are needed when keyborad is serviced, ISR will do that just fine.

Ioannis

[mpgmike]

Darrel Taylor's Instant Interrupts (DT_INTs) changed things for the PBP world. PBP Interrupts are Polled, not actually using the built-in Interrupt hardware. Using ASM somewhat defeated the reason to buy PBP in the first place. Earlier PICs stayed with standardized naming conventions, Bank selection, and Bank location of SFRs. Newer PICs gave new names to familiar peripherals; like changing TMR2 to T2TMR for example. The newer PICxxQyy PICs even changed the default Bank from BANK0 to BANK4. No wonder DT_INTs no longer worked.

A small group of us dove into the ASM behind the scenes for the DT_INTs and uncovered the working mechanisms. By changing naming, BANK locations of SFRs, and a few other things, we were able to get the incredible DT_INTs working on newer offerings. The good news is that a collaborative effort spells out what these changes entail, and how you can do it too. This body of work is available in The Book of DT's Interrupts.

[Ioannis]

It is not very easy or straightforward to make a new or modify the existing file and cover a new chip.

At least for me. Just did a mess and gave up. I really do not follow what the DT-INTS does, so it is difficult to succesfully make a new chip addition. Wish there were step by step instructions for this.

Ioannis

[mpgmike]

Did you look at the DT Book of Interrupts linked 2 posts ago? In fact, the main page lists you as one of the contributors. The part I contributed focused on what to change to add new chips. Take a look (or a refresher).

[Ioannis]

I guess you mean this article:

https://dt.picbasic.co.uk/INT16/Customisation

I am pretty sure that did something stupid and the modified interrupt did not work as expected. Ended to make a poll of the interrupt bit and finished my project.

OK, will give it a try again. With a bottle of coffee this time!

Ioannis

P.S. The 18 series requires modifications in 2 places. Why is that? Because of the priorities?

[tumbleweed]

The 18 series requires modifications in 2 places. Why is that? Because of the priorities?

The first one creates a '#define' used by the INT_LIST, INT_ENABLE and other macros that specifies the PIR reg and bit

  #define INT1_INT  INTCON3,INT1IF  ;-- INT1 External

The second one adds all the details (PIR intr reg/bit, PIE enable reg/bit, and IPR priority reg/bit)

  ifdef INT1IF
      INT_Source  INTCON3,INT1IF, INTCON3,INT1IE, INTCON3,INT1IP
  endif

If you're lucky, that's all that's required. However, some of the newer devices like the 18FxxK42 and 18FxxQ43 required some serious modifications to the asm code to make DT_INTS compatible with the register layout and new instructions like MOVFFL, so the 'customization guide' isn't much help with them.

[Ioannis]

Well, these are the chips I want to have DT_INTS work with...! Among a few others.

Ioannis

[tumbleweed]

Here's a version of DT-INTS that works with all the 18xv core devices (K42, K83, and Q43)
It could be used to add the Q83/Q84 and Q40/Q41, but those can't be used by PBP since they're not supported by the stock version of MPASMX
(there are pbp device files for the Q84 but they don't work).

If you want support for them (and a few others) you'll have to switch to using Swordfish, which has all the new 18F's.

The zip file contains DT_INTS-18xv.bas and two versions of ReEnterPBP (ReEnterPBP-18xv.bas, ReEnterPBP-18xvLP.bas) to go along with it.
Read the comments at the beginning of DT_INTS-18xv for details, especially the part about setting 'CONFIG MVECEN = OFF'

[Ioannis]

Many many thanks for these files!

The Q83/Q84 and Q40/Q41 devices are very nice ones, but yeah, will not be supported, too pity.

Ioannis