Hello thronborg,
You will find in your Directory named MPASM suite text files representing every PIC covered by that version of mpasm, and in these text files lie ALL the registers and config fuses available to that particular chip. From the P16F887 file you will find the following:
Code:
;----- CONFIG1 Options --------------------------------------------------
_LP_OSC EQU H'3FF8' ; LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
_XT_OSC EQU H'3FF9' ; XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
_HS_OSC EQU H'3FFA' ; HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
_EC_OSC EQU H'3FFB' ; EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
_INTRC_OSC_NOCLKOUT EQU H'3FFC' ; INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
_INTOSCIO EQU H'3FFC' ; INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
_INTRC_OSC_CLKOUT EQU H'3FFD' ; INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
_INTOSC EQU H'3FFD' ; INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
_EXTRC_OSC_NOCLKOUT EQU H'3FFE' ; RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
_EXTRCIO EQU H'3FFE' ; RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
_EXTRC_OSC_CLKOUT EQU H'3FFF' ; RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
_EXTRC EQU H'3FFF' ; RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
_WDT_OFF EQU H'3FF7' ; WDT disabled and can be enabled by SWDTEN bit of the WDTCON register
_WDT_ON EQU H'3FFF' ; WDT enabled
_PWRTE_ON EQU H'3FEF' ; PWRT enabled
_PWRTE_OFF EQU H'3FFF' ; PWRT disabled
_MCLRE_OFF EQU H'3FDF' ; RE3/MCLR pin function is digital input, MCLR internally tied to VDD
_MCLRE_ON EQU H'3FFF' ; RE3/MCLR pin function is MCLR
_CP_ON EQU H'3FBF' ; Program memory code protection is enabled
_CP_OFF EQU H'3FFF' ; Program memory code protection is disabled
_CPD_ON EQU H'3F7F' ; Data memory code protection is enabled
_CPD_OFF EQU H'3FFF' ; Data memory code protection is disabled
_BOR_OFF EQU H'3CFF' ; BOR disabled
_BOR_SBODEN EQU H'3DFF' ; BOR controlled by SBOREN bit of the PCON register
_BOR_NSLEEP EQU H'3EFF' ; BOR enabled during operation and disabled in Sleep
_BOR_ON EQU H'3FFF' ; BOR enabled
_IESO_OFF EQU H'3BFF' ; Internal/External Switchover mode is disabled
_IESO_ON EQU H'3FFF' ; Internal/External Switchover mode is enabled
_FCMEN_OFF EQU H'37FF' ; Fail-Safe Clock Monitor is disabled
_FCMEN_ON EQU H'3FFF' ; Fail-Safe Clock Monitor is enabled
_LVP_OFF EQU H'2FFF' ; RB3 pin has digital I/O, HV on MCLR must be used for programming
_LVP_ON EQU H'3FFF' ; RB3/PGM pin has PGM function, low voltage programming enabled
_DEBUG_ON EQU H'1FFF' ; In_Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
_DEBUG_OFF EQU H'3FFF' ; In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
;----- CONFIG2 Options --------------------------------------------------
_BOR21V EQU H'3EFF' ; Brown-out Reset set to 2.1V
_BOR40V EQU H'3FFF' ; Brown-out Reset set to 4.0V
_WRT_HALF EQU H'39FF' ; 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control
_WRT_1FOURTH EQU H'3BFF' ; 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control
_WRT_256 EQU H'3DFF' ; 0000h to 00FFh write protected, 0100h to 1FFFh may be modified by EECON control
_WRT_OFF EQU H'3FFF' ; Write protection off
;----- DEVID Equates --------------------------------------------------
_DEVID1 EQU H'2006'
;----- IDLOC Equates --------------------------------------------------
_IDLOC0 EQU H'2000'
_IDLOC1 EQU H'2001'
_IDLOC2 EQU H'2002'
_IDLOC3 EQU H'2003'
For the 16F688:
Code:
_BOD_OFF EQU H'3CFF' ; BOR disabled
_BOR_OFF EQU H'3CFF' ; BOR disabled
_BOD_SBODEN EQU H'3DFF' ; BOR controlled by SBOREN bit of the PCON register
_BOR_SBODEN EQU H'3DFF' ; BOR controlled by SBOREN bit of the PCON register
_BOD_NSLEEP EQU H'3EFF' ; BOR enabled during operation and disabled in Sleep
_BOR_NSLEEP EQU H'3EFF' ; BOR enabled during operation and disabled in Sleep
_BOD_ON EQU H'3FFF' ; BOR enabled
_BOR_ON EQU H'3FFF' ; BOR enabled
Be aware many of these chips have multiple config, config1 config2, and the appropriate configs must attach to the config numbers where they are listed (the 887 is one of those). See the listing above, notice the _bor21v in the config2 listing . . .
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