I have been grabbing for straws for about 20 hours on this. I have two 18F2525s working together and using 4 lines of DIO to do signal a few different states between the two. The issue I have boils down to this: One 2525 has PortC.0-PortC.3 each going directly to the gate of a NIF5003NT1G. The other 2525 runs several devices through SEROUT2/SERIN2. The problem I am running into is that when the code gets to the point of setting the TRISC registers for those four pins to "0" it disrupts the LCD screen the other PIC is running. I am guessing I am missing some configuration bit and the pins are creating noise on the PCB when they are configured as an output. Can anybody look at this quickly and tell me if they see something obvious? I don't want to post all the code for both PICs as well as the PCB layout because if the problem is that deep then it is beyond the scope of the help I should be seeking on this forum and I should just be hiring somebody to do this for me. Thanks in advance.
osccon = %10000010 'this changes to internal 32khz
#CONFIG
CONFIG IESO = OFF
CONFIG OSC = INTIO67
CONFIG PWRT = ON
CONFIG BOREN = SBORDIS
CONFIG BORV = 3
CONFIG WDT = OFF
CONFIG WDTPS = 2048
CONFIG CCP2MX = PORTC
CONFIG PBADEN = OFF
CONFIG LPT1OSC = OFF
CONFIG MCLRE = OFF
CONFIG STVREN = ON
CONFIG LVP = OFF
CONFIG XINST = OFF
CONFIG DEBUG = OFF
#ENDCONFIG
CMCON = 7
ADCON1 = %00001111
CCP1CON = %00000000
T1CON = %00000100
T3CON = %00000100
SSPCON1 = %00000101
LOW PORTC.6
PAUSEUS 50
Port1MOS var portc.0
Port2MOS var portc.1
Port3MOS var portc.2
Port4MOS var portc.3
Port1sense var porta.0
Port2sense var porta.1
Port3sense var porta.2
Port4sense var porta.3
trisa.5 = 1
trisc.0 = 0
trisc.1 = 0
trisc.2 = 0
trisc.3 = 0
trisa.0 = 1
trisa.1 = 1
trisa.2 = 1
trisa.3 = 1
'DEFINE OSC 40
'do
'loop
do
if port1sense = 0 or port2sense = 0 or port3sense = 0 or port4sense = 0 then
high portc.6 'goes to b.3 on master
pause 1
endif
if port1sense = 1 and port2sense = 1 and port3sense = 1 and port4sense = 1 then
low portc.6
pause 1
endif
if porta.5 = 1 then 'goes to a.5 on master
high portc.0
high portc.1
high portc.2
high portc.3
endif
if porta.5 = 0 then
low portc.0
low portc.1
low portc.2
low portc.3
endif
loop
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