Hi,
With the BIG caps on your board something Hurts me :
14.5 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
V
DD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to V
DD
through an RC network, as described in
. A maximum rise time for VDD is specified.
See
Section 17.0 “Electrical Characteristics” for
details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating conditions
are met.
looks there's a missing cap in your design ... don't you think ???
On my side, I use MC34064P5 supervisor to get rid of power on or reset rise times ... and have NO issues with reset pin ...
BTW ... a hardware reset after reading the Prog memory is not to forget ...
Alain
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