PIC with Automatic Context Saving

[Dick Ivers]

As a matter of curiosity I recently tested a 16F1828 device. This is one of the newer PICs having interrupt capability with automatic context saving. In this case, the new device replaced a 16F690, a 20 pin chip with the same pinout. The original PBP program (too long to include here) incorporates a DT_INT utility to service a change on porta.1 interrupt. The actual functioning circuit works well and as expected.

With the 16F1828 software I removed all the DT_INT stuff, and rewrote the program in PBP to include a DEFINE INTHAND pointing to a short ASM handler routine. Didn't do much else ... the new device took care of context saving. With this in place the circuit again worked well. The difference was that the new program complied with 625 fewer program words. This may be of interest in situations where you are tight on code space.

[Ioannis]

Why not post he new code for members to have it as a reference?

Ioannis

[Acetronics2]

Hi, Ioannis

That looks like simply using asm interrupts as stated in the 9.3 Chapter of the Manual ...

as it is a 4k memory device ... PBP will include the context saving stubb by itself ... like for the elder devices ...

nothing exceptionnal here ...

Alain

[Dick Ivers]

delete --------

[Bruce]

Does PBP automatically insert a context saving stub for enhanced 14-bit core types, and does chapter 9.3 apply to these..

I thought the post was pretty helpful, but do agree it would be more helpful to show how he structured his .asm int handler.

[Acetronics2]

Hi, Bruce

I had read the relevant chapter of the Databook ...

8.5 Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these registers
are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications
to any of these registers are desired, the corresponding
Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s application,

other registers may also need to be saved

Was not so clear from me ... I do agree !!!

just meant : it is like for other 4K devices, No need to care about asm Context saving ...

But the really interesting point is, RESTORING is done by itself ... a contrario than elder devices ...

Ok ... no need to reserve RAM nor ...

...

Alain