OSCON setting for 18F4520

[Dennis]

Hi all

Just a quick question regarding the OSCON setting in an 18F4520 PIC

Here are my settings currently

'Ocsillator selections here
OSCCON = $70 'Int CLK 8MHz
OSCTUNE.6 = 1 'PLL 4x
ADCON1= %00001111 '$0F = disable A/D converter
cmcon = 7
INTCON2.7 = 0 'switch pull-ups ON
'END of oscillator selections
'timer/oscillator defines
DEFINE OSC 32 '4x 8MHz
'END of timer/oscillator defines

I have read through the datasheet and undertstand how the internal clock works and the various clock settings and so forth...BUT ... what I can't make sense of or remember is why my OSCON value is $70 ..is this REVERSED HEX 70 as per the required register setting ?
So binary would be 1110000 ?
And if I wanted 4 MHz the setting would be $60 or 0110000 not so ?

In the datasheet there is a bit to set internal clock as stable or not, ie 0 or 1 ..does anyone have a recommendation for that one ?

Kind regards
Dennis

[mackrackit]

DEFINE OSC 8
OSCCON=%01110000
or
DEFINE OSC 4
OSCCON=%01100000

OSCTUNE.6 = 1 'PLL 4x
does not do PLL. As far as I know PLL is not possible with the internal OSC.

The other OSCON bits leave at zero, they are for reading.

[rmteo]

.... As far as I know PLL is not possible with the internal OSC.

From the datasheet (DS39631A):

2.5.2 PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock output
of up to 32 MHz.

2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the internal
oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency
is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.

[ScaleRobotics]

I have read through the datasheet and undertstand how the internal clock works and the various clock settings and so forth...BUT ... what I can't make sense of or remember is why my OSCON value is $70 ..is this REVERSED HEX 70 as per the required register setting ?
So binary would be 1110000 ?
And if I wanted 4 MHz the setting would be $60 or 0110000 not so ?

In the datasheet there is a bit to set internal clock as stable or not, ie 0 or 1 ..does anyone have a recommendation for that one ?

Hello Dennis,

$70 hex is 01110000 binary, and $60 hex is 01100000 binary, so yes I think you have got it. That would be 8mhz and 4mhz respectively.

The stability bit is a read only bit. It tells you when the oscillator is stable again, as you could change your oscillator frequency in software.

The PLL does work for internal oscillator. See section 2.6.4 of the data sheet.

[mackrackit]

Thanks for the correction.
The data sheet for the 18F4550 does not have the sections you referred to.
DOH!!!

Time to check my glasses...

[Dennis]

First of all thanks all of you for your replies, thoughts and guidance :-)

All postings have raised a few questions though ...

 DEFINE OSC 8
OSCCON=%01110000
or
DEFINE OSC 4
OSCCON=%01100000

OSCTUNE.6 = 1 'PLL 4x

So far we know ..according to the datasheet that PLL is only available if we run at 4MHz or 8MHz and the PLL bit is enabled.

With this in mind, if your desired frequency is either 4 or 8 MHz , you probably want to make sure that OSCTUNE.6=0 since this would disable the PLL setting.
So the above code settings for 4 or 8MHz would be as follows

 DEFINE OSC 8
OSCCON=%01110000
or
DEFINE OSC 4
OSCCON=%01100000

OSCTUNE.6 = 0 'PLL Multiplier disabled

And thats as per this in the datasheet

Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output fre-
quency is either 4MHz or 8MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
s disabled.
The PLLEN control bit is only functional in those inter-
nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.

Am I correct ?
Kind regards
Dennis

[Dennis]

Just another thought..

Can you achieve 20MHz then ?

Can the PLL multiplier be altered to achieve 20MHz maybe ?

Dennis

[Melanie]

The PLL multiplyer will multiply x4 whatever your OSCILLATOR is running at. There are no other options... it's either x4 or OFF.

You need a 5MHz Crystal or Resonator if you want 20MHz using the PLL Multiplier.

The Internal Oscillator does not have 5MHz as one of it's selectable options (neither does it have 20MHz).

So if you WANT 20MHz, you'll need a 20MHz Xtal or Resonator, use HS Mode and have the PLL multiplier OFF (or 5MHz Xtal or Resonator, HS Mode and have the PLL multiplyer ON).

Section 2, Datasheet DS39631A explains it in great detail (for the 18F4520 chip) which you said you were using at the start of this thread.

[Dennis]

Thank Melanie and everyone else who replied to this thread !

It is all CRYSTAL CLEAR now !!
:-)

Thank a million