Presetting Configuration Fuses (PIC Defines) into your Program

Hello
I am new to this forum, I am a RF Engineer trying to use a 18F1220 with its internal oscillator. So far I have been unsucessfull in doing this. When using MPLAB and a IDC2 in debugger mode the Blink program works fine. When I program the device and run it on its own power it does not work. I think I traced it to the 18f1220.inc file, CONFIG1H fuse.

;************************************************* ***************
;* 18F1220.INC *
;* *
;* By : Leonard Zerman, Jeff Schmoyer *
;* Notice : Copyright (c) 2004 microEngineering Labs, Inc. *
;* All Rights Reserved *
;* Date : 01/27/04 *
;* Version : 2.45 *
;* Notes : *
;************************************************* ***************
NOLIST
ifdef PM_USED
LIST
"Error: PM does not support this device. Use MPASM."
NOLIST
else
LIST
LIST p = 18F1220, r = dec, w = -311, f = inhx32
INCLUDE "P18F1220.INC" ; MPASM Header
__CONFIG _CONFIG1H, _XT_OSC_1H
__CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
__CONFIG _CONFIG3H, _MCLRE_ON_3H
__CONFIG _CONFIG4L, _LVP_OFF_4L
NOLIST
endif
LIST
EEPROM_START EQU 0F00000h
BLOCK_SIZE EQU 8

It sets the oscillator to External. I am not sure what the fuse should be set to. I also beleve the INTRC needs to be reconfigured for 8 MHz. Can anyone assist me? Thank You.

Quote:

---

Originally Posted by wbubel

Hello
I am new to this forum, I am a RF Engineer trying to use a 18F1220 with its internal oscillator. So far I have been unsucessfull in doing this. When using MPLAB and a IDC2 in debugger mode the Blink program works fine. When I program the device and run it on its own power it does not work. I think I traced it to the 18f1220.inc file, CONFIG1H fuse.

;************************************************* ***************
;* 18F1220.INC *
;* *
;* By : Leonard Zerman, Jeff Schmoyer *
;* Notice : Copyright (c) 2004 microEngineering Labs, Inc. *
;* All Rights Reserved *
;* Date : 01/27/04 *
;* Version : 2.45 *
;* Notes : *
;************************************************* ***************
NOLIST
ifdef PM_USED
LIST
"Error: PM does not support this device. Use MPASM."
NOLIST
else
LIST
LIST p = 18F1220, r = dec, w = -311, f = inhx32
INCLUDE "P18F1220.INC" ; MPASM Header
__CONFIG _CONFIG1H, _XT_OSC_1H
__CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
__CONFIG _CONFIG3H, _MCLRE_ON_3H
__CONFIG _CONFIG4L, _LVP_OFF_4L
NOLIST
endif
LIST
EEPROM_START EQU 0F00000h
BLOCK_SIZE EQU 8

It sets the oscillator to External. I am not sure what the fuse should be set to. I also beleve the INTRC needs to be reconfigured for 8 MHz. Can anyone assist me? Thank You.

---

Hello wbubel, Welcome !
In the MPASM Suite each supported PIC has a file, named for it I. E. P18F1220.inc, in it is listed every valid config and register address. To switch to using MPASM, in MCS click view, compile and program options,click on the tab named assembler, and insert a check in the box "use MPASM", click OK and you are set. Here is what is available for config 1 . . .

Code:

---

;Configuration Byte 1H Options
_IESO_ON_1H      EQU  H'FF' ; Internal External Oscillator Switch Over mode enabled
_IESO_OFF_1H      EQU  H'7F' ; Internal External Oscillator Switch Over mode disabled
_FSCM_ON_1H      EQU  H'FF' ; Fail-Safe Clock Monitor enabled
_FSCM_OFF_1H      EQU  H'BF' ; Fail-Safe Clock Monitor disabled
_RC_OSC_1H        EQU  H'FF' ; External RC on OSC1, OSC2 as FOSC/4
_RCIO_OSC_1H      EQU  H'F7' ; External RC on OSC1, OSC2 as RA6
_LP_OSC_1H        EQU  H'F0' ; LP Oscillator
_XT_OSC_1H        EQU  H'F1' ; XT Oscillator
_HS_OSC_1H        EQU  H'F2' ; HS Oscillator
_HSPLL_OSC_1H    EQU  H'F6' ; HS + PLL
_EC_OSC_1H        EQU  H'F4' ; External Clock on OSC1, OSC2 as FOSC/4
_ECIO_OSC_1H      EQU  H'F5' ; External Clock on OSC1, OSC2 as RA6
_INTIO1_OSC_1H    EQU  H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4
_INTIO2_OSC_1H    EQU  H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6

---

You can change it in the file you posted or comment them out there and just add the ones you want at the top of your code (my preferred method). Most PICs you use DEFINE OSC 8 , but I won't say all . . .

_INTIO2_OSC_1H would set it for internal osc with OSC1 & OSC2 pins free to use for I/O.

Look in the P18F1220.INC file in your MPLAB directory for a list of config options.

To select 8MHz internal, look in the 18F1220 data sheet in the Oscillator Configurations
section. It shows the value to write to OSCCON to select various frequencies.

When programming the PIC with the ICD, in inserts a debug kernel, so you may need to
configure the ICD as the programmer before burning the PIC for stand-alone operation.

With the ICD debug kernel programmed into the PIC it needs the PC interface to operate.

Joe S. and Bruce
Thanks for your valuable help. Sorry its been a while since I've been able to get back to this project. Here is the status. I have set the CONFIG1H fuse to
_INTIO2_OSC_1H as Bruce suggested and OSCCON = %01110000.
I set the ICD as a programmer. When I released the PIC from Reset it runs so slow I thought it was not working. Either I screwed up the OSCCON settings or there is something I am missing.


OSCCON = %01110000 'Define the Osc to 8 MHz
LED2 var PORTB.2 ' LED
cntr var word
FET var PORTA.0
TRISA = %00000000 ' Set PORTA ports 0-4 to input, 5-7 Output
TRISB = %00000000 ' Set PORTB to all output
PORTB = %00000100 ' Clear PORTB
PORTA = %00000000 ' Clear PORTA

cntr = 0
FET = 0

Main:
led2 = 1
pause 100
led2 = 0
pause 100
' cntr = cntr + 1
' if (cntr <= 2) then goto main
' FET = 1
goto main
Stop

Can anyone Help me.

Quote:

---

Originally Posted by wbubel

I set the ICD as a programmer. When I released the PIC from Reset it runs so slow I thought it was not working. Either I screwed up the OSCCON settings or there is something I am missing.

---

You should compile NOT using ICD COMPILE, use the one which says compile, only use ICD compile to use the ICD, recompile with the COMPILE for stand alone use. Put a
DEFINE OSC 4
or whatever number is right in you code near the top. The PIC is probably running using the fail safe oscillator .

This piece of code made it work

DEFINE OSC 4 'Define the Osc to 8 MHz

asm
bsf OSCCON, SCS1 ; 1x = Internal Block
bcf OSCCON, SCS0 ; 00 = Primary Oscillator (20Mhz?)
bsf OSCCON, IRCF2 ; 111=8000 110=4000 101=2000
bsf OSCCON, IRCF1 ; 100=1000 011=0500 010=0250
bcf OSCCON, IRCF0 ; 001=0125 000=0032
MSTABLE010 btfss OSCCON, IOFS
bra MSTABLE010 ; wait until Oscillator is stable
endasm

This doesn't directly apply to your situation this time, but I did run into a sneaky change the other day that took me a while to notice..
I was trying to change the oscillator config on a 18F1320. I had been recently using 18F1330s and just assumed they would be the same since they were so close family wise. Bad assumption. Here are the two together.

Code:

---

;****************************************************************
;*  18F1330.INC                                                *
;*                                                              *
;*  By        : Leonard Zerman, Jeff Schmoyer                  *
;*  Notice    : Copyright (c) 2006 microEngineering Labs, Inc.  *
;*              All Rights Reserved                            *
;*  Date      : 06/05/06                                        *
;*  Version  : 2.47                                            *
;*  Notes    :                                                *
;****************************************************************
        NOLIST
    ifdef PM_USED
        LIST
        "Error: PM does not support this device.  Use MPASM."
        NOLIST
    else
        LIST
        LIST p = 18F1330, r = dec, w = -311, w = -230, f = inhx32
        INCLUDE "P18F1330.INC"  ; MPASM  Header
        __CONFIG    _CONFIG1H, _OSC_INTIO2_1H
      ; __CONFIG    _CONFIG1H, _OSC_XT_1H
        __CONFIG    _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
        __CONFIG    _CONFIG4L, _XINST_OFF_4L
        NOLIST
    endif
        LIST
EEPROM_START        EQU        0F00000h
BLOCK_SIZE        EQU        8

'==============================================================================
'==============================================================================

;****************************************************************
;*  18F1320.INC                                                *
;*                                                              *
;*  By        : Leonard Zerman, Jeff Schmoyer                  *
;*  Notice    : Copyright (c) 2006 microEngineering Labs, Inc.  *
;*              All Rights Reserved                            *
;*  Date      : 06/05/06                                        *
;*  Version  : 2.47                                            *
;*  Notes    :                                                *
;****************************************************************
        NOLIST
    ifdef PM_USED
        LIST
        "Error: PM does not support this device.  Use MPASM."
        NOLIST
    else
        LIST
        LIST p = 18F1320, r = dec, w = -311, w = -230, f = inhx32
        INCLUDE "P18F1320.INC"  ; MPASM  Header
        __CONFIG    _CONFIG1H, _INTIO2_OSC_1H    ; this for INT OSC
    ;  __CONFIG    _CONFIG1H, _XT_OSC_1H        ;was this for XT OSC
        __CONFIG    _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
        __CONFIG    _CONFIG4L, _LVP_OFF_4L
        NOLIST
    endif
        LIST
EEPROM_START        EQU        0F00000h
BLOCK_SIZE        EQU        8

---

the commented out part was my addition, but notice the different syntax for the oscillator statement.
Just hadn't run into that before.
Bo

Hi all,

I have tried to find where the @MyConfig references were without any success. Anyone have them bookmarked?
I still don't have a good handle on changing these without tweaking the .inc files and I'm afraid that's going to bite me someday (even though I do leave the original lines REM'd).

I have seen @MyConfig used, but don't know if there are any caveats.

Thanks
Bo

Hi Bo,
@__Config MyConfig was something Darrel came up with for me, so as to be able to put the config statements on several lines. This was so I could see them without having to scroll across some 100 or so places on the screen. I have MCS set up with large fonts as I have rather poor vision. You still have to comment out the default configs and place the correct configs in your code. It simply allows you to put them on multiple lines. Search for my posts and you will find examples of it's use. If you need examples I can post some Saturday after my new cable internet connection get's hooked up, until then I am not at home while in here.
JS

Okay, I've rummaged through the manual, looked at several old threads, and at the "include" files for the device (16F88). I've carefully read through Melanie's post on the subject http://www.picbasic.co.uk/forum/show...16&postcount=1

Whatever occurs after @_config generates error 122 ("illegal opcode"). It also appears that _INTRC_IO doesn't want to fly. I'm using MPASM.

Maybe I've not found the right thread yet.

<i><b>HELP!</b></i>

I don't think it's what's after it, it's the config...

@ __config _CONFIG1, _xxxx
That's @ space two(2) underscores config space "the _CONFIG? word" comma etc...
Only 1 underscore for the config word and options.
<br>

Yep, it was the double underscore. Then I commented out the line in the INC file, and everything is peachy-keeno.

Thanks!

HI.

WHAT DO YOU MEAN WITH THE FOLLOWING?

don't forget to comment the PBP default fuse.

Quote:

---

Originally Posted by brianD

HI.

WHAT DO YOU MEAN WITH THE FOLLOWING?

don't forget to comment the PBP default fuse.

---

Did you read the whole thread???

So I notice that some 18F chips have the old style configs like CONFIG1H, as well as the new style listed in their chipx.inc file. But other chips, like the 18F26J50 only have the new style, with no CONFIG1H style in the Microchip .inc file for that chip.

I have read the configs have been depreciated posts, where Darrel says ignore the warnings, they are just that ... warnings. However, with newer chips like the PIC18F26J50, is there a way to get around the error:
Error[176]c:\picbasic\26j50-~.asm 101 :CONFIG Directive Error: (setting "48" not found for the processor 18F26J50) ? It seems so close, to only be held up by defining the oscillator!

I get the above error when I try to use :

Code:

---

DEFINE OSC 48
ASM
  CONFIG OSC=HSPLL
  CONFIG CPUDIV=OSC1
  CONFIG PLLDIV=5
  CONFIG LPT1OSC=OFF
  CONFIG CP0=OFF
  CONFIG WDTEN=ON
  CONFIG XINST=OFF
  CONFIG IOL1WAY=OFF
  CONFIG STVREN=OFF
  CONFIG T1DIG=ON
  CONFIG FCMEN=OFF
  CONFIG WDTPS=512
  CONFIG RTCOSC=T1OSCREF
ENDASM

---

If I comment out the DEFINE OSC 48, all appears good. If I try to define the OSC setting, I get the 176 error.

..there are no CONFIG1H's here...

Code:

---

;==========================================================================
;
;  IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
;              superseded by the CONFIG directive.  The following settings
;              are available for this device.
;
;  Watchdog Timer:
;    WDTEN = OFF          Disabled - Controlled by SWDTEN bit
;    WDTEN = ON          Enabled
;
;  PLL Prescaler Selection bits:
;    PLLDIV = 12          Divide by 12 (48 MHz oscillator input)
;    PLLDIV = 10          Divide by 10 (40 MHz oscillator input)
;    PLLDIV = 6          Divide by 6 (24 MHz oscillator input)
;    PLLDIV = 5          Divide by 5 (20 MHz oscillator input)
;    PLLDIV = 4          Divide by 4 (16 MHz oscillator input)
;    PLLDIV = 3          Divide by 3 (12 MHz oscillator input)
;    PLLDIV = 2          Divide by 2 (8 MHz oscillator input)
;    PLLDIV = 1          No prescale (4 MHz oscillator input drives PLL directly)
;
;  Stack Overflow/Underflow Reset :
;    STVREN = OFF        Disabled
;    STVREN = ON          Enabled
;
;  Extended Instruction Set:
;    XINST = OFF          Disabled
;    XINST = ON          Enabled
;
;  CPU System Clock Postscaler:
;    CPUDIV = OSC4_PLL6  CPU system clock divide by 6
;    CPUDIV = OSC3_PLL3  CPU system clock divide by 3
;    CPUDIV = OSC2_PLL2  CPU system clock divide by 2
;    CPUDIV = OSC1        No CPU system clock divide
;
;  Code Protect:
;    CP0 = ON            Program memory is code-protected
;    CP0 = OFF            Program memory is not code-protected
;
;  Oscillator:
;    OSC = INTOSC        INTOSC
;    OSC = INTOSCO        INTOSCO (CLKO-RA6)
;    OSC = INTOSCPLL      INTOSCPLL
;    OSC = INTOSCPLLO    INTOSCPLLO (CLKO-RA6)
;    OSC = HS            HS, USB-HS
;    OSC = HSPLL          HS+PLL, USB-HS+PLL
;    OSC = EC            EC (CLKO-RA6), USB-EC
;    OSC = ECPLL          EC+PLL (CLKO-RA6), USB-EC+PLL
;
;  T1OSCEN Enforcement:
;    T1DIG = OFF          Secondary Oscillator clock source may not be selected
;    T1DIG = ON          Secondary Oscillator clock source may be selected
;
;  Low-Power Timer1 Oscillator:
;    LPT1OSC = ON        Low-power operation
;    LPT1OSC = OFF        High-power operation
;
;  Fail-Safe Clock Monitor:
;    FCMEN = OFF          Disabled
;    FCMEN = ON          Enabled
;
;  Internal External Oscillator Switch Over Mode:
;    IESO = OFF          Disabled
;    IESO = ON            Enabled
;
;  Watchdog Postscaler:
;    WDTPS = 1            1:1
;    WDTPS = 2            1:2
;    WDTPS = 4            1:4
;    WDTPS = 8            1:8
;    WDTPS = 16          1:16
;    WDTPS = 32          1:32
;    WDTPS = 64          1:64
;    WDTPS = 128          1:128
;    WDTPS = 256          1:256
;    WDTPS = 512          1:512
;    WDTPS = 1024        1:1024
;    WDTPS = 2048        1:2048
;    WDTPS = 4096        1:4096
;    WDTPS = 8192        1:8192
;    WDTPS = 16384        1:16384
;    WDTPS = 32768        1:32768
;
;  DSWDT Clock Select:
;    DSWDTOSC = T1OSCREF  DSWDT uses T1OSC/T1CKI
;    DSWDTOSC = INTOSCREF DSWDT uses INTRC
;
;  RTCC Clock Select:
;    RTCOSC = INTOSCREF  RTCC uses INTRC
;    RTCOSC = T1OSCREF    RTCC uses T1OSC/T1CKI
;
;  Deep Sleep BOR:
;    DSBOREN = OFF        Disabled
;    DSBOREN = ON        Enabled
;
;  Deep Sleep Watchdog Timer:
;    DSWDTEN = OFF        Disabled
;    DSWDTEN = ON        Enabled
;
;  Deep Sleep Watchdog Postscaler:
;    DSWDTPS = 2          1:2 (2.1 ms)
;    DSWDTPS = 8          1:8 (8.3 ms)
;    DSWDTPS = 32        1:32 (33 ms)
;    DSWDTPS = 128        1:128 (132 ms)
;    DSWDTPS = 512        1:512 (528 ms)
;    DSWDTPS = 2048      1:2,048 (2.1 seconds)
;    DSWDTPS = 8192      1:8,192 (8.5 seconds)
;    DSWDTPS = K32        1:32,768 (34 seconds)
;    DSWDTPS = K131      1:131,072 (135 seconds)
;    DSWDTPS = K524      1:524,288 (9 minutes)
;    DSWDTPS = M2        1:2,097,152 (36 minutes)
;    DSWDTPS = M8        1:8,388,608 (2.4 hours)
;    DSWDTPS = M33        1:33,554,432 (9.6 hours)
;    DSWDTPS = M134      1:134,217,728 (38.5 hours)
;    DSWDTPS = M536      1:536,870,912 (6.4 days)
;    DSWDTPS = G2        1:2,147,483,648 (25.7 days)
;
;  IOLOCK One-Way Set Enable bit:
;    IOL1WAY = OFF        The IOLOCK bit (PPSCON<0>) can be set and cleared as needed
;    IOL1WAY = ON        The IOLOCK bit (PPSCON<0>) can be set once
;
;  MSSP address masking:
;    MSSP7B_EN = MSK5    5 Bit address masking mode
;    MSSP7B_EN = MSK7    7 Bit address masking mode
;
;  Write/Erase Protect Page Start/End Location:
;    WPFP = PAGE_0        Write Protect Program Flash Page 0
;    WPFP = PAGE_1        Write Protect Program Flash Page 1
;    WPFP = PAGE_2        Write Protect Program Flash Page 2
;    WPFP = PAGE_3        Write Protect Program Flash Page 3
;    WPFP = PAGE_4        Write Protect Program Flash Page 4
;    WPFP = PAGE_5        Write Protect Program Flash Page 5
;    WPFP = PAGE_6        Write Protect Program Flash Page 6
;    WPFP = PAGE_7        Write Protect Program Flash Page 7
;    WPFP = PAGE_8        Write Protect Program Flash Page 8
;    WPFP = PAGE_9        Write Protect Program Flash Page 9
;    WPFP = PAGE_10      Write Protect Program Flash Page 10
;    WPFP = PAGE_11      Write Protect Program Flash Page 11
;    WPFP = PAGE_12      Write Protect Program Flash Page 12
;    WPFP = PAGE_13      Write Protect Program Flash Page 13
;    WPFP = PAGE_14      Write Protect Program Flash Page 14
;    WPFP = PAGE_15      Write Protect Program Flash Page 15
;    WPFP = PAGE_16      Write Protect Program Flash Page 16
;    WPFP = PAGE_17      Write Protect Program Flash Page 17
;    WPFP = PAGE_18      Write Protect Program Flash Page 18
;    WPFP = PAGE_19      Write Protect Program Flash Page 19
;    WPFP = PAGE_20      Write Protect Program Flash Page 20
;    WPFP = PAGE_21      Write Protect Program Flash Page 21
;    WPFP = PAGE_22      Write Protect Program Flash Page 22
;    WPFP = PAGE_23      Write Protect Program Flash Page 23
;    WPFP = PAGE_24      Write Protect Program Flash Page 24
;    WPFP = PAGE_25      Write Protect Program Flash Page 25
;    WPFP = PAGE_26      Write Protect Program Flash Page 26
;    WPFP = PAGE_27      Write Protect Program Flash Page 27
;    WPFP = PAGE_28      Write Protect Program Flash Page 28
;    WPFP = PAGE_29      Write Protect Program Flash Page 29
;    WPFP = PAGE_30      Write Protect Program Flash Page 30
;    WPFP = PAGE_31      Write Protect Program Flash Page 31
;    WPFP = PAGE_32      Write Protect Program Flash Page 32
;    WPFP = PAGE_33      Write Protect Program Flash Page 33
;    WPFP = PAGE_34      Write Protect Program Flash Page 34
;    WPFP = PAGE_35      Write Protect Program Flash Page 35
;    WPFP = PAGE_36      Write Protect Program Flash Page 36
;    WPFP = PAGE_37      Write Protect Program Flash Page 37
;    WPFP = PAGE_38      Write Protect Program Flash Page 38
;    WPFP = PAGE_39      Write Protect Program Flash Page 39
;    WPFP = PAGE_40      Write Protect Program Flash Page 40
;    WPFP = PAGE_41      Write Protect Program Flash Page 41
;    WPFP = PAGE_42      Write Protect Program Flash Page 42
;    WPFP = PAGE_43      Write Protect Program Flash Page 43
;    WPFP = PAGE_44      Write Protect Program Flash Page 44
;    WPFP = PAGE_45      Write Protect Program Flash Page 45
;    WPFP = PAGE_46      Write Protect Program Flash Page 46
;    WPFP = PAGE_47      Write Protect Program Flash Page 47
;    WPFP = PAGE_48      Write Protect Program Flash Page 48
;    WPFP = PAGE_49      Write Protect Program Flash Page 49
;    WPFP = PAGE_50      Write Protect Program Flash Page 50
;    WPFP = PAGE_51      Write Protect Program Flash Page 51
;    WPFP = PAGE_52      Write Protect Program Flash Page 52
;    WPFP = PAGE_53      Write Protect Program Flash Page 53
;    WPFP = PAGE_54      Write Protect Program Flash Page 54
;    WPFP = PAGE_55      Write Protect Program Flash Page 55
;    WPFP = PAGE_56      Write Protect Program Flash Page 56
;    WPFP = PAGE_57      Write Protect Program Flash Page 57
;    WPFP = PAGE_58      Write Protect Program Flash Page 58
;    WPFP = PAGE_59      Write Protect Program Flash Page 59
;    WPFP = PAGE_60      Write Protect Program Flash Page 60
;    WPFP = PAGE_61      Write Protect Program Flash Page 61
;    WPFP = PAGE_62      Write Protect Program Flash Page 62
;    WPFP = PAGE_63      Write Protect Program Flash Page 63
;
;  Write/Erase Protect Region Select bit (valid when WPDIS = 0):
;    WPEND = PAGE_0      Page 0 to WPFP<5:0> erase/write-protected
;    WPEND = PAGE_WPFP    Pages WPFP<5:0> to (Configuration Words page) write/erase protected
;
;  Write/Erase Protect Configuration Region :
;    WPCFG = ON          Configuration Words page erase/write-protected
;    WPCFG = OFF          Configuration Words page not erase/write-protected
;
;  Write Protect Disable bit:
;    WPDIS = ON          WPFP[5:0], WPEND, and WPCFG bits enabled
;    WPDIS = OFF          WPFP[5:0], WPEND, and WPCFG bits ignored
;
;==========================================================================
_DEVID1          EQU  H'3FFFFE'
_DEVID2          EQU  H'3FFFFF'

---

Is the only solution is to edit all configs in the PBP include file, or am I missing something. If this has already been covered, let me have it....


I notice that the 18F4550 has both styles in it's include file, like this:

Code:

---

;==========================================================================
;
;  IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
;              superseded by the CONFIG directive.  The following settings
;              are available for this device.
;
;  PLL Prescaler Selection bits:
;    PLLDIV = 1          No prescale (4 MHz oscillator input drives PLL directly)
;    PLLDIV = 2          Divide by 2 (8 MHz oscillator input)
;    PLLDIV = 3          Divide by 3 (12 MHz oscillator input)
;    PLLDIV = 4          Divide by 4 (16 MHz oscillator input)
;    PLLDIV = 5          Divide by 5 (20 MHz oscillator input)
;    PLLDIV = 6          Divide by 6 (24 MHz oscillator input)
;    PLLDIV = 10          Divide by 10 (40 MHz oscillator input)
;    PLLDIV = 12          Divide by 12 (48 MHz oscillator input)
;
;  CPU System Clock Postscaler:
;    CPUDIV = OSC1_PLL2  [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
;    CPUDIV = OSC2_PLL3  [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
;    CPUDIV = OSC3_PLL4  [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
;    CPUDIV = OSC4_PLL6  [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
;
;  USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):
;    USBDIV = 1          USB clock source comes directly from the primary oscillator block with no postscale
;    USBDIV = 2          USB clock source comes from the 96 MHz PLL divided by 2
;
;  Oscillator Selection bits:
;    FOSC = XT_XT        XT oscillator, XT used by USB
;    FOSC = XTPLL_XT      XT oscillator, PLL enabled, XT used by USB
;    FOSC = ECIO_EC      External clock, port function on RA6, EC used by USB
;    FOSC = EC_EC        External clock, CLKOUT on RA6, EC used by USB
;    FOSC = ECPLLIO_EC    External clock, PLL enabled, port function on RA6, EC used by USB
;    FOSC = ECPLL_EC      External clock, PLL enabled, CLKOUT on RA6, EC used by USB
;    FOSC = INTOSCIO_EC  Internal oscillator, port function on RA6, EC used by USB
;    FOSC = INTOSC_EC    Internal oscillator, CLKOUT on RA6, EC used by USB
;    FOSC = INTOSC_XT    Internal oscillator, XT used by USB
;    FOSC = INTOSC_HS    Internal oscillator, HS used by USB
;    FOSC = HS            HS oscillator, HS used by USB
;    FOSC = HSPLL_HS      HS oscillator, PLL enabled, HS used by USB
;
;  Fail-Safe Clock Monitor Enable bit:
;    FCMEN = OFF          Fail-Safe Clock Monitor disabled
;    FCMEN = ON          Fail-Safe Clock Monitor enabled
;
;  Internal/External Oscillator Switchover bit:
;    IESO = OFF          Oscillator Switchover mode disabled
;    IESO = ON            Oscillator Switchover mode enabled
;
;  Power-up Timer Enable bit:
;    PWRT = ON            PWRT enabled
;    PWRT = OFF          PWRT disabled
;
;  Brown-out Reset Enable bits:
;    BOR = OFF            Brown-out Reset disabled in hardware and software
;    BOR = SOFT          Brown-out Reset enabled and controlled by software (SBOREN is enabled)
;    BOR = ON_ACTIVE      Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
;    BOR = ON            Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
;  Brown-out Voltage bits:
;    BORV = 0            Maximum setting
;    BORV = 1           
;    BORV = 2           
;    BORV = 3            Minimum setting
;
;  USB Voltage Regulator Enable bit:
;    VREGEN = OFF        USB voltage regulator disabled
;    VREGEN = ON          USB voltage regulator enabled
;
;  Watchdog Timer Enable bit:
;    WDT = OFF            HW Disabled - SW Controlled
;    WDT = ON            HW Enabled - SW Disabled
;
;  Watchdog Timer Postscale Select bits:
;    WDTPS = 1            1:1
;    WDTPS = 2            1:2
;    WDTPS = 4            1:4
;    WDTPS = 8            1:8
;    WDTPS = 16          1:16
;    WDTPS = 32          1:32
;    WDTPS = 64          1:64
;    WDTPS = 128          1:128
;    WDTPS = 256          1:256
;    WDTPS = 512          1:512
;    WDTPS = 1024        1:1024
;    WDTPS = 2048        1:2048
;    WDTPS = 4096        1:4096
;    WDTPS = 8192        1:8192
;    WDTPS = 16384        1:16384
;    WDTPS = 32768        1:32768
;
;  MCLR Pin Enable bit:
;    MCLRE = OFF          RE3 input pin enabled; MCLR disabled
;    MCLRE = ON          MCLR pin enabled; RE3 input pin disabled
;
;  Low-Power Timer 1 Oscillator Enable bit:
;    LPT1OSC = OFF        Timer1 configured for higher power operation
;    LPT1OSC = ON        Timer1 configured for low-power operation
;
;  PORTB A/D Enable bit:
;    PBADEN = OFF        PORTB<4:0> pins are configured as digital I/O on Reset
;    PBADEN = ON          PORTB<4:0> pins are configured as analog input channels on Reset
;
;  CCP2 MUX bit:
;    CCP2MX = OFF        CCP2 input/output is multiplexed with RB3
;    CCP2MX = ON          CCP2 input/output is multiplexed with RC1
;
;  Stack Full/Underflow Reset Enable bit:
;    STVREN = OFF        Stack full/underflow will not cause Reset
;    STVREN = ON          Stack full/underflow will cause Reset
;
;  Single-Supply ICSP Enable bit:
;    LVP = OFF            Single-Supply ICSP disabled
;    LVP = ON            Single-Supply ICSP enabled
;
;  Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit:
;    ICPRT = OFF          ICPORT disabled
;    ICPRT = ON          ICPORT enabled
;
;  Extended Instruction Set Enable bit:
;    XINST = OFF          Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
;    XINST = ON          Instruction set extension and Indexed Addressing mode enabled
;
;  Background Debugger Enable bit:
;    DEBUG = ON          Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
;    DEBUG = OFF          Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
;  Code Protection bit Block 0:
;    CP0 = ON            Block 0 (000800-001FFFh) code-protected
;    CP0 = OFF            Block 0 (000800-001FFFh) not code-protected
;
;  Code Protection bit Block 1:
;    CP1 = ON            Block 1 (002000-003FFFh) code-protected
;    CP1 = OFF            Block 1 (002000-003FFFh) not code-protected
;
;  Code Protection bit Block 2:
;    CP2 = ON            Block 2 (004000-005FFFh) code-protected
;    CP2 = OFF            Block 2 (004000-005FFFh) not code-protected
;
;  Code Protection bit Block 3:
;    CP3 = ON            Block 3 (006000-007FFFh) code-protected
;    CP3 = OFF            Block 3 (006000-007FFFh) not code-protected
;
;  Boot Block Code Protection bit:
;    CPB = ON            Boot block (000000-0007FFh) code-protected
;    CPB = OFF            Boot block (000000-0007FFh) not code-protected
;
;  Data EEPROM Code Protection bit:
;    CPD = ON            Data EEPROM code-protected
;    CPD = OFF            Data EEPROM not code-protected
;
;  Write Protection bit Block 0:
;    WRT0 = ON            Block 0 (000800-001FFFh) write-protected
;    WRT0 = OFF          Block 0 (000800-001FFFh) not write-protected
;
;  Write Protection bit Block 1:
;    WRT1 = ON            Block 1 (002000-003FFFh) write-protected
;    WRT1 = OFF          Block 1 (002000-003FFFh) not write-protected
;
;  Write Protection bit Block 2:
;    WRT2 = ON            Block 2 (004000-005FFFh) write-protected
;    WRT2 = OFF          Block 2 (004000-005FFFh) not write-protected
;
;  Write Protection bit Block 3:
;    WRT3 = ON            Block 3 (006000-007FFFh) write-protected
;    WRT3 = OFF          Block 3 (006000-007FFFh) not write-protected
;
;  Boot Block Write Protection bit:
;    WRTB = ON            Boot block (000000-0007FFh) write-protected
;    WRTB = OFF          Boot block (000000-0007FFh) not write-protected
;
;  Configuration Register Write Protection bit:
;    WRTC = ON            Configuration registers (300000-3000FFh) write-protected
;    WRTC = OFF          Configuration registers (300000-3000FFh) not write-protected
;
;  Data EEPROM Write Protection bit:
;    WRTD = ON            Data EEPROM write-protected
;    WRTD = OFF          Data EEPROM not write-protected
;
;  Table Read Protection bit Block 0:
;    EBTR0 = ON          Block 0 (000800-001FFFh) protected from table reads executed in other blocks
;    EBTR0 = OFF          Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
;
;  Table Read Protection bit Block 1:
;    EBTR1 = ON          Block 1 (002000-003FFFh) protected from table reads executed in other blocks
;    EBTR1 = OFF          Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
;
;  Table Read Protection bit Block 2:
;    EBTR2 = ON          Block 2 (004000-005FFFh) protected from table reads executed in other blocks
;    EBTR2 = OFF          Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
;
;  Table Read Protection bit Block 3:
;    EBTR3 = ON          Block 3 (006000-007FFFh) protected from table reads executed in other blocks
;    EBTR3 = OFF          Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
;
;  Boot Block Table Read Protection:
;    EBTRB = ON          Boot block (000000-0007FFh) protected from table reads executed in other blocks
;    EBTRB = OFF          Boot block (000000-0007FFh) not protected from table reads executed in other blocks
;
;==========================================================================
;==========================================================================
;
;      Configuration Bits
;
;  NAME            Address
;  CONFIG1L        300000h
;  CONFIG1H        300001h
;  CONFIG2L        300002h
;  CONFIG2H        300003h
;  CONFIG3H        300005h
;  CONFIG4L        300006h
;  CONFIG5L        300008h
;  CONFIG5H        300009h
;  CONFIG6L        30000Ah
;  CONFIG6H        30000Bh
;  CONFIG7L        30000Ch
;  CONFIG7H        30000Dh
;
;==========================================================================

; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1L        EQU  H'300000'
_CONFIG1H        EQU  H'300001'
_CONFIG2L        EQU  H'300002'
_CONFIG2H        EQU  H'300003'
_CONFIG3H        EQU  H'300005'
_CONFIG4L        EQU  H'300006'
_CONFIG5L        EQU  H'300008'
_CONFIG5H        EQU  H'300009'
_CONFIG6L        EQU  H'30000A'
_CONFIG6H        EQU  H'30000B'
_CONFIG7L        EQU  H'30000C'
_CONFIG7H        EQU  H'30000D'

;----- CONFIG1L Options --------------------------------------------------
_PLLDIV_1_1L        EQU  H'F8'    ; No prescale (4 MHz oscillator input drives PLL directly)
_PLLDIV_2_1L        EQU  H'F9'    ; Divide by 2 (8 MHz oscillator input)
_PLLDIV_3_1L        EQU  H'FA'    ; Divide by 3 (12 MHz oscillator input)
_PLLDIV_4_1L        EQU  H'FB'    ; Divide by 4 (16 MHz oscillator input)
_PLLDIV_5_1L        EQU  H'FC'    ; Divide by 5 (20 MHz oscillator input)
_PLLDIV_6_1L        EQU  H'FD'    ; Divide by 6 (24 MHz oscillator input)
_PLLDIV_10_1L        EQU  H'FE'    ; Divide by 10 (40 MHz oscillator input)
_PLLDIV_12_1L        EQU  H'FF'    ; Divide by 12 (48 MHz oscillator input)

_CPUDIV_OSC1_PLL2_1L EQU  H'E7'    ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
_CPUDIV_OSC2_PLL3_1L EQU  H'EF'    ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
_CPUDIV_OSC3_PLL4_1L EQU  H'F7'    ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
_CPUDIV_OSC4_PLL6_1L EQU  H'FF'    ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]

_USBDIV_1_1L        EQU  H'DF'    ; USB clock source comes directly from the primary oscillator block with no postscale
_USBDIV_2_1L        EQU  H'FF'    ; USB clock source comes from the 96 MHz PLL divided by 2

;----- CONFIG1H Options --------------------------------------------------
_FOSC_XT_XT_1H      EQU  H'F0'    ; XT oscillator, XT used by USB
_FOSC_XTPLL_XT_1H    EQU  H'F2'    ; XT oscillator, PLL enabled, XT used by USB
_FOSC_ECIO_EC_1H    EQU  H'F4'    ; External clock, port function on RA6, EC used by USB
_FOSC_EC_EC_1H      EQU  H'F5'    ; External clock, CLKOUT on RA6, EC used by USB
_FOSC_ECPLLIO_EC_1H  EQU  H'F6'    ; External clock, PLL enabled, port function on RA6, EC used by USB
_FOSC_ECPLL_EC_1H    EQU  H'F7'    ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB
_FOSC_INTOSCIO_EC_1H EQU  H'F8'    ; Internal oscillator, port function on RA6, EC used by USB
_FOSC_INTOSC_EC_1H  EQU  H'F9'    ; Internal oscillator, CLKOUT on RA6, EC used by USB
_FOSC_INTOSC_XT_1H  EQU  H'FA'    ; Internal oscillator, XT used by USB
_FOSC_INTOSC_HS_1H  EQU  H'FB'    ; Internal oscillator, HS used by USB
_FOSC_HS_1H          EQU  H'FC'    ; HS oscillator, HS used by USB
_FOSC_HSPLL_HS_1H    EQU  H'FE'    ; HS oscillator, PLL enabled, HS used by USB

_FCMEN_OFF_1H        EQU  H'BF'    ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H        EQU  H'FF'    ; Fail-Safe Clock Monitor enabled

_IESO_OFF_1H        EQU  H'7F'    ; Oscillator Switchover mode disabled
_IESO_ON_1H          EQU  H'FF'    ; Oscillator Switchover mode enabled

;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L          EQU  H'FE'    ; PWRT enabled
_PWRT_OFF_2L        EQU  H'FF'    ; PWRT disabled

_BOR_OFF_2L          EQU  H'F9'    ; Brown-out Reset disabled in hardware and software
_BOR_SOFT_2L        EQU  H'FB'    ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOR_ON_ACTIVE_2L    EQU  H'FD'    ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOR_ON_2L          EQU  H'FF'    ; Brown-out Reset enabled in hardware only (SBOREN is disabled)

_BORV_0_2L          EQU  H'E7'    ; Maximum setting
_BORV_1_2L          EQU  H'EF'    ;
_BORV_2_2L          EQU  H'F7'    ;
_BORV_3_2L          EQU  H'FF'    ; Minimum setting

_VREGEN_OFF_2L      EQU  H'DF'    ; USB voltage regulator disabled
_VREGEN_ON_2L        EQU  H'FF'    ; USB voltage regulator enabled

;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H          EQU  H'FE'    ; HW Disabled - SW Controlled
_WDT_ON_2H          EQU  H'FF'    ; HW Enabled - SW Disabled

_WDTPS_1_2H          EQU  H'E1'    ; 1:1
_WDTPS_2_2H          EQU  H'E3'    ; 1:2
_WDTPS_4_2H          EQU  H'E5'    ; 1:4
_WDTPS_8_2H          EQU  H'E7'    ; 1:8
_WDTPS_16_2H        EQU  H'E9'    ; 1:16
_WDTPS_32_2H        EQU  H'EB'    ; 1:32
_WDTPS_64_2H        EQU  H'ED'    ; 1:64
_WDTPS_128_2H        EQU  H'EF'    ; 1:128
_WDTPS_256_2H        EQU  H'F1'    ; 1:256
_WDTPS_512_2H        EQU  H'F3'    ; 1:512
_WDTPS_1024_2H      EQU  H'F5'    ; 1:1024
_WDTPS_2048_2H      EQU  H'F7'    ; 1:2048
_WDTPS_4096_2H      EQU  H'F9'    ; 1:4096
_WDTPS_8192_2H      EQU  H'FB'    ; 1:8192
_WDTPS_16384_2H      EQU  H'FD'    ; 1:16384
_WDTPS_32768_2H      EQU  H'FF'    ; 1:32768

;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H        EQU  H'7F'    ; RE3 input pin enabled; MCLR disabled
_MCLRE_ON_3H        EQU  H'FF'    ; MCLR pin enabled; RE3 input pin disabled

_LPT1OSC_OFF_3H      EQU  H'FB'    ; Timer1 configured for higher power operation
_LPT1OSC_ON_3H      EQU  H'FF'    ; Timer1 configured for low-power operation

_PBADEN_OFF_3H      EQU  H'FD'    ; PORTB<4:0> pins are configured as digital I/O on Reset
_PBADEN_ON_3H        EQU  H'FF'    ; PORTB<4:0> pins are configured as analog input channels on Reset

_CCP2MX_OFF_3H      EQU  H'FE'    ; CCP2 input/output is multiplexed with RB3
_CCP2MX_ON_3H        EQU  H'FF'    ; CCP2 input/output is multiplexed with RC1

;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L      EQU  H'FE'    ; Stack full/underflow will not cause Reset
_STVREN_ON_4L        EQU  H'FF'    ; Stack full/underflow will cause Reset

_LVP_OFF_4L          EQU  H'FB'    ; Single-Supply ICSP disabled
_LVP_ON_4L          EQU  H'FF'    ; Single-Supply ICSP enabled

_ICPRT_OFF_4L        EQU  H'DF'    ; ICPORT disabled
_ICPRT_ON_4L        EQU  H'FF'    ; ICPORT enabled

_XINST_OFF_4L        EQU  H'BF'    ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L        EQU  H'FF'    ; Instruction set extension and Indexed Addressing mode enabled

_DEBUG_ON_4L        EQU  H'7F'    ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L        EQU  H'FF'    ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L          EQU  H'FE'    ; Block 0 (000800-001FFFh) code-protected
_CP0_OFF_5L          EQU  H'FF'    ; Block 0 (000800-001FFFh) not code-protected

_CP1_ON_5L          EQU  H'FD'    ; Block 1 (002000-003FFFh) code-protected
_CP1_OFF_5L          EQU  H'FF'    ; Block 1 (002000-003FFFh) not code-protected

_CP2_ON_5L          EQU  H'FB'    ; Block 2 (004000-005FFFh) code-protected
_CP2_OFF_5L          EQU  H'FF'    ; Block 2 (004000-005FFFh) not code-protected

_CP3_ON_5L          EQU  H'F7'    ; Block 3 (006000-007FFFh) code-protected
_CP3_OFF_5L          EQU  H'FF'    ; Block 3 (006000-007FFFh) not code-protected

;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H          EQU  H'BF'    ; Boot block (000000-0007FFh) code-protected
_CPB_OFF_5H          EQU  H'FF'    ; Boot block (000000-0007FFh) not code-protected

_CPD_ON_5H          EQU  H'7F'    ; Data EEPROM code-protected
_CPD_OFF_5H          EQU  H'FF'    ; Data EEPROM not code-protected

;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L          EQU  H'FE'    ; Block 0 (000800-001FFFh) write-protected
_WRT0_OFF_6L        EQU  H'FF'    ; Block 0 (000800-001FFFh) not write-protected

_WRT1_ON_6L          EQU  H'FD'    ; Block 1 (002000-003FFFh) write-protected
_WRT1_OFF_6L        EQU  H'FF'    ; Block 1 (002000-003FFFh) not write-protected

_WRT2_ON_6L          EQU  H'FB'    ; Block 2 (004000-005FFFh) write-protected
_WRT2_OFF_6L        EQU  H'FF'    ; Block 2 (004000-005FFFh) not write-protected

_WRT3_ON_6L          EQU  H'F7'    ; Block 3 (006000-007FFFh) write-protected
_WRT3_OFF_6L        EQU  H'FF'    ; Block 3 (006000-007FFFh) not write-protected

;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H          EQU  H'BF'    ; Boot block (000000-0007FFh) write-protected
_WRTB_OFF_6H        EQU  H'FF'    ; Boot block (000000-0007FFh) not write-protected

_WRTC_ON_6H          EQU  H'DF'    ; Configuration registers (300000-3000FFh) write-protected
_WRTC_OFF_6H        EQU  H'FF'    ; Configuration registers (300000-3000FFh) not write-protected

_WRTD_ON_6H          EQU  H'7F'    ; Data EEPROM write-protected
_WRTD_OFF_6H        EQU  H'FF'    ; Data EEPROM not write-protected

;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L        EQU  H'FE'    ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
_EBTR0_OFF_7L        EQU  H'FF'    ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks

_EBTR1_ON_7L        EQU  H'FD'    ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
_EBTR1_OFF_7L        EQU  H'FF'    ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks

_EBTR2_ON_7L        EQU  H'FB'    ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
_EBTR2_OFF_7L        EQU  H'FF'    ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks

_EBTR3_ON_7L        EQU  H'F7'    ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks
_EBTR3_OFF_7L        EQU  H'FF'    ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks

;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H        EQU  H'BF'    ; Boot block (000000-0007FFh) protected from table reads executed in other blocks
_EBTRB_OFF_7H        EQU  H'FF'    ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks

---

Thanks,

Walter

Hi Walter,

When using the new config directives you need to place them in the 18F26J50.INC file. They will not work when dropped directly in your code file.

Thanks Bruce,

The configs work. My configuration fuses get changed properly, my led blinks. However, PBP can not accept the speed of my oscillator. It looks like the only thing that needs to be done is to have MeLabs make some sort of change on their end to accept the OSC speed.

Hi Walter,

Are you setting OSCTUNE.6 to enable the 96MHz multiplier?

Hi Bruce,

I had it in some earlier code, but you are right it is missing here. That brings me back up to what appears to be 12 x the 4 mhz default speed (that is 12x faster than PBP is expecting it, since I am missing the define to make it compile), when I leave out my oscillator define. But when I put in my DEFINE OSC XX I get the same error as before.

I'm guessing you still have the new config directives in your code VS in the 18F26J50.INC file?
That will cause the error. You need to place these in your 18F26J50.INC file.

Then it should work as expected.

Yes, I do. My question sort of was:

Is there a work around. Sounds like the answer is NO for the newer chips that do not have the CONFIGxL/H in their .inc file.

Which brings me to my next question:
Since it appears that the only hang up is the way PBP checks to see if you can run at the processor speed, do you think this can be fixed pretty easily by MeLabs? Or do you think I am making it out to be easier than it really is. I have tried to do a work-around, but have not succeeded (yet).

It is not such a big deal, as I can declare them as you suggest. But I am stubborn, and it appears to be one single register that needs to be set, and it would work.

I'm not sure what the fix would be to be honest, but if you're up for an experiment, try this;

Make a backup copy of your PBPPIC18.LIB.

Now use an editor to find & replace all instances of OSC with XTAL.

Save the .LIB file, and compile with DEFINE XTAL 48, and the new config directives in your code.

Does it work?

Thanks Bruce, that does the trick! Just did exactly as you said, and now it lets me compile inside my program code like this:

Code:

---

Define XTAL 48
OSCTUNE.6 =1
ASM
  CONFIG OSC=HSPLL
  CONFIG CPUDIV=OSC1
  CONFIG PLLDIV=5
  CONFIG LPT1OSC=OFF
  CONFIG CP0=OFF
  CONFIG WDTEN=ON
  CONFIG XINST=OFF
  CONFIG IOL1WAY=OFF
  CONFIG STVREN=OFF
  CONFIG T1DIG=ON
  CONFIG FCMEN=OFF
  CONFIG WDTPS=512
  CONFIG RTCOSC=T1OSCREF
ENDASM

---

And my LED is blinking at the right speed. Yes, I could just edit configs in the .inc file, but then you have to change it for each project. A pain if you want to jump around from unfinished project to unfinished project. Oh, that's just me.... :D

Cool. Maybe the fix is something as simple as melabs changing to something other than OSC?

Just bear-in-mind that your next PBP update will change everything, and any patch will fail since you've modified your library files...;o)

Ah, I see what you mean!

Code:

---

Define XTAL 48
OSCTUNE.6 =1
ASM
  CONFIG OSC=HSPLL

---

I got this error: overwriting previous address contents (2007)
I write this line @ __CONFIG _INTRC_OSC_NOCLKOUT to turn on the internal oscilator of the PIC16F628A,
I fix any mistakes what I think I made them,but there are errors.I DEFINE OSC 4,it's not working.

You need to comment the *.inc file for the chip in the PBP directory.
http://www.picbasic.co.uk/forum/show...=6775#post6775

I get: Unable to open INCLUDE file P16F628A.INC

Quote:

---

Originally Posted by SKOLS1

I get: Unable to open INCLUDE file P16F628A.INC

---

Be sure Microcode Studio knows where that file is located. Click view, Compile and Program Options ,click the assembler tab,check USE MPASM, and Click either find Manually or Find Automatically.

Quote:

---

Originally Posted by Archangel

Be sure Microcode Studio knows where that file is located. Click view, Compile and Program Options ,click the assembler tab,check USE MPASM, and Click either find Manually or Find Automatically.

---

I try with P16F628.INF file and It isn't working with another Include file(16F628.inc).I find it automatically but still not working.I will try with my other computer.I am using MPLAB IDE v8.73,I have those problems with MPLAB IDE v.7.60.What do you think?

You do not include those files, PBP does that for you. All you need to do is tell PBP where MPASM is.
http://www.picbasic.co.uk/forum/cont...tudio-PICKIT-2

Oh , it's been 7 years and this thread is still hot!
Here is my configuration problem using PIC12F1822.

As long as i red the manuals i guess the correct is

@ __CONFIG1 _FOSC_INTOSC & _<blah blah>

but... GAGA:chargrined: ... wrong.
i also tried

@ __CONFIG _FOSC_INTOSC & _<blah blah>

also tried include the .inc neither worked.

Any ideas?
Thanks in advance! :surprise:.

These configs are for the PM assembler.

Which assembler are you using? Also which version of PBP?

The inc is not to be included. But you can open it and see what are the configuration words exaclty.

I would recommend using MPASM as an assembler and the syntax of your compiler.

Ioannis

Nop ,
these configs are for the MPASM assembler - which i use ,
since PM (of the PBP 2.60c i use) does not support the 12F1822.

ps. just saw you're from Thessaloniki too :)
so , Kalo Sabbatokyriako ! 'Good Weekend

Ooops yes, thats is MPASM but the syntax was not correct.

Try this

Code:

---

ASM
  __config _CONFIG1, _FOSC_INTOSC
ENDASM


---

Yes, I am located in Thessaloniki :)

Ioannis

Overwriting previous address contents (8007) :(

Problem solved!

I had to use

ASM
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_19 & _LVP_OFF

ENDASM

and the trick was to ";" comment out the __CONFIG in M12F1822.INC file in the PBP directory , because it conflicted.

Here are a few examples of how to use the new #CONFIG block syntax for PBP3. (This will NOT work on previous versions of PBP ... Get your upgrade now :) )

PBP3 makes it a little easier to figure out, and set up your configs. It has eliminated the need to comment out the default configurations set up by PBP. It still has default settings - these can be found in the /PBP3/DEVICES file under yourchip.PBPINC . Here is an example of default settings for the PIC18F45K22:

Code:

---

; CUT rest of file out for display purposes

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  The #CONFIG block is passed directly to the asm file, but PBP will replace it
;  automagically with the contents of a user-defined #CONFIG block if one is
;  found in the PBP source program.

#CONFIG
        __CONFIG    _CONFIG1H, _FOSC_INTIO67_1H
        __CONFIG    _CONFIG3H, _PBADEN_OFF_3H
        __CONFIG    _CONFIG4L, _LVP_OFF_4L & _XINST_OFF_4L
#ENDCONFIG

; CUT rest of file out for display purposes

---

If you want to change the default configs in PBP3, DON'T edit the above file. You can just declare them in your code using the #CONFIG #ENDCONFIG block. For all the possibilities of config settings for your chip, check out the /PBP3/DEVICE_REFERENCE folder, and select the yourchip.INFO file. It will look something like this:

Code:

---


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;  File:    PIC18F45K22.INFO
;  Date:    07/24/11
;  Generated by melabs File Manager
;
;  PICBASIC PRO(tm) Compiler version: 3.0.0.x
;
;  Copyright 2011 microEngineering Labs, Inc.  All Rights Reserved
;  The content herein is intended to facilitate embedded development using
;  PICBASIC PRO Compiler.  Reproduction or utilization for other purposes
;  is prohibited without written permission from microEngineering Labs, Inc..
; 
;  microEngineering Labs, Inc.
;  2845 Ore Mill Road STE 4
;  Colorado Springs, CO  80904
;  719-520-5323
;  fax: 719-520-1867
;  http://melabs.com
;  [email protected]
;
;  Modifications to this file in the \DEVICE_REFERENCE folder will be overwritten when
;  you install future upgrades.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;MPASM CONFIG Directive Options
;
;  This section is included for reference only.  The following options may
;  be used with the MPASM CONFIG directive to specify configuration settings
;  in the source program using the #CONFIG/#ENDCONFIG block.
;  Example:
;
;  #CONFIG
;    CONFIG  OSC = HS
;    CONFIG  WDTE = ON
;  #ENDCONFIG
;
;
;  Oscillator Selection bits
;    CONFIG FOSC = RC        ;111X External RC oscillator, CLKOUT function on RA6
;    CONFIG FOSC = ECLPIO6        ;EC oscillator (low power, <500 kHz)
;    CONFIG FOSC = ECLP        ;EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz)
;    CONFIG FOSC = ECMPIO6        ;EC oscillator (medium power, 500 kHz-16 MHz)
;    CONFIG FOSC = ECMP        ;EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)
;    CONFIG FOSC = INTIO7        ;Internal oscillator block, CLKOUT function on OSC2
;    CONFIG FOSC = INTIO67        ;Internal oscillator block
;    CONFIG FOSC = RCIO6        ;External RC oscillator
;    CONFIG FOSC = RC        ;External RC oscillator, CLKOUT function on OSC2
;    CONFIG FOSC = ECHPIO6        ;EC oscillator (high power, >16 MHz)
;    CONFIG FOSC = ECHP        ;EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
;    CONFIG FOSC = HSMP        ;HS oscillator (medium power 4-16 MHz)
;    CONFIG FOSC = HSHP        ;HS oscillator (high power > 16 MHz)
;    CONFIG FOSC = XT        ;XT oscillator
;    CONFIG FOSC = LP        ;LP oscillator
;
;  4X PLL Enable
;    CONFIG PLLCFG = OFF        ;Oscillator used directly
;    CONFIG PLLCFG = ON        ;Oscillator multiplied by 4
;
;  Primary clock enable bit
;    CONFIG PRICLKEN = OFF        ;Primary clock can be disabled by software
;    CONFIG PRICLKEN = ON        ;Primary clock is always enabled
;
;  Fail-Safe Clock Monitor Enable bit
;    CONFIG FCMEN = OFF        ;Fail-Safe Clock Monitor disabled
;    CONFIG FCMEN = ON        ;Fail-Safe Clock Monitor enabled
;
;  Internal/External Oscillator Switchover bit
;    CONFIG IESO = OFF        ;Oscillator Switchover mode disabled
;    CONFIG IESO = ON        ;Oscillator Switchover mode enabled
;
;  Power-up Timer Enable bit
;    CONFIG PWRTEN = OFF        ;Power up timer disabled
;    CONFIG PWRTEN = ON        ;Power up timer enabled
;
;  Brown-out Reset Enable bits
;    CONFIG BOREN = SBORDIS        ;Brown-out Reset enabled in hardware only (SBOREN is disabled)
;    CONFIG BOREN = NOSLP        ;Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
;    CONFIG BOREN = ON        ;Brown-out Reset enabled and controlled by software (SBOREN is enabled)
;    CONFIG BOREN = OFF        ;Brown-out Reset disabled in hardware and software
;
;  Brown Out Reset Voltage bits
;    CONFIG BORV = 190        ;VBOR set to 1.90 V nominal
;    CONFIG BORV = 220        ;VBOR set to 2.20 V nominal
;    CONFIG BORV = 250        ;VBOR set to 2.50 V nominal
;    CONFIG BORV = 285        ;VBOR set to 2.85 V nominal
;
;  Watchdog Timer Enable bits
;    CONFIG WDTEN = ON        ;WDT is always enabled. SWDTEN bit has no effect
;    CONFIG WDTEN = SWON        ;WDT is controlled by SWDTEN bit of the WDTCON register
;    CONFIG WDTEN = NOSLP        ;WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
;    CONFIG WDTEN = OFF        ;Watch dog timer is always disabled. SWDTEN has no effect.
;
;  Watchdog Timer Postscale Select bits
;    CONFIG WDTPS = 32768        ;1:32768
;    CONFIG WDTPS = 16384        ;1:16384
;    CONFIG WDTPS = 8192        ;1:8192
;    CONFIG WDTPS = 4096        ;1:4096
;    CONFIG WDTPS = 2048        ;1:2048
;    CONFIG WDTPS = 1024        ;1:1024
;    CONFIG WDTPS = 512        ;1:512
;    CONFIG WDTPS = 256        ;1:256
;    CONFIG WDTPS = 128        ;1:128
;    CONFIG WDTPS = 64        ;1:64
;    CONFIG WDTPS = 32        ;1:32
;    CONFIG WDTPS = 16        ;1:16
;    CONFIG WDTPS = 8        ;1:8
;    CONFIG WDTPS = 4        ;1:4
;    CONFIG WDTPS = 2        ;1:2
;    CONFIG WDTPS = 1        ;1:1
;
;  CCP2 MUX bit
;    CONFIG CCP2MX = PORTC1        ;CCP2 input/output is multiplexed with RC1
;    CONFIG CCP2MX = PORTB3        ;CCP2 input/output is multiplexed with RB3
;
;  PORTB A/D Enable bit
;    CONFIG PBADEN = ON        ;PORTB<5:0> pins are configured as analog input channels on Reset
;    CONFIG PBADEN = OFF        ;PORTB<5:0> pins are configured as digital I/O on Reset
;
;  P3A/CCP3 Mux bit
;    CONFIG CCP3MX = PORTB5        ;P3A/CCP3 input/output is multiplexed with RB5
;    CONFIG CCP3MX = PORTE0        ;P3A/CCP3 input/output is mulitplexed with RE0
;
;  HFINTOSC Fast Start-up
;    CONFIG HFOFST = ON        ;HFINTOSC output and ready status are not delayed by the oscillator stable status
;    CONFIG HFOFST = OFF        ;HFINTOSC output and ready status are delayed by the oscillator stable status
;
;  Timer3 Clock input mux bit
;    CONFIG T3CMX = PORTC0        ;T3CKI is on RC0
;    CONFIG T3CMX = PORTB5        ;T3CKI is on RB5
;
;  ECCP2 B output mux bit
;    CONFIG P2BMX = PORTD2        ;P2B is on RD2
;    CONFIG P2BMX = PORTC0        ;P2B is on RC0
;
;  MCLR Pin Enable bit
;    CONFIG MCLRE = EXTMCLR        ;MCLR pin enabled, RE3 input pin disabled
;    CONFIG MCLRE = INTMCLR        ;RE3 input pin enabled; MCLR disabled
;
;  Stack Full/Underflow Reset Enable bit
;    CONFIG STVREN = ON        ;Stack full/underflow will cause Reset
;    CONFIG STVREN = OFF        ;Stack full/underflow will not cause Reset
;
;  Single-Supply ICSP Enable bit
;    CONFIG LVP = ON        ;Single-Supply ICSP enabled if MCLRE is also 1
;    CONFIG LVP = OFF        ;Single-Supply ICSP disabled
;
;  Extended Instruction Set Enable bit
;    CONFIG XINST = ON        ;Instruction set extension and Indexed Addressing mode enabled
;    CONFIG XINST = OFF        ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
;
;  Background Debug
;    CONFIG DEBUG = OFF        ;Disabled
;    CONFIG DEBUG = ON        ;Enabled
;
;  Code Protection Block 0
;    CONFIG CP0 = OFF        ;Block 0 (000800-001FFFh) not code-protected
;    CONFIG CP0 = ON        ;Block 0 (000800-001FFFh) code-protected
;
;  Code Protection Block 1
;    CONFIG CP1 = OFF        ;Block 1 (002000-003FFFh) not code-protected
;    CONFIG CP1 = ON        ;Block 1 (002000-003FFFh) code-protected
;
;  Code Protection Block 2
;    CONFIG CP2 = OFF        ;Block 2 (004000-005FFFh) not code-protected
;    CONFIG CP2 = ON        ;Block 2 (004000-005FFFh) code-protected
;
;  Code Protection Block 3
;    CONFIG CP3 = OFF        ;Block 3 (006000-007FFFh) not code-protected
;    CONFIG CP3 = ON        ;Block 3 (006000-007FFFh) code-protected
;
;  Boot Block Code Protection bit
;    CONFIG CPB = OFF        ;Boot block (000000-0007FFh) not code-protected
;    CONFIG CPB = ON        ;Boot block (000000-0007FFh) code-protected
;
;  Data EEPROM Code Protection bit
;    CONFIG CPD = OFF        ;Data EEPROM not code-protected
;    CONFIG CPD = ON        ;Data EEPROM code-protected
;
;  Write Protection Block 0
;    CONFIG WRT0 = OFF        ;Block 0 (000800-001FFFh) not write-protected
;    CONFIG WRT0 = ON        ;Block 0 (000800-001FFFh) write-protected
;
;  Write Protection Block 1
;    CONFIG WRT1 = OFF        ;Block 1 (002000-003FFFh) not write-protected
;    CONFIG WRT1 = ON        ;Block 1 (002000-003FFFh) write-protected
;
;  Write Protection Block 2
;    CONFIG WRT2 = OFF        ;Block 2 (004000-005FFFh) not write-protected
;    CONFIG WRT2 = ON        ;Block 2 (004000-005FFFh) write-protected
;
;  Write Protection Block 3
;    CONFIG WRT3 = OFF        ;Block 3 (006000-007FFFh) not write-protected
;    CONFIG WRT3 = ON        ;Block 3 (006000-007FFFh) write-protected
;
;  Configuration Register Write Protection bit
;    CONFIG WRTC = OFF        ;Configuration registers (300000-3000FFh) not write-protected
;    CONFIG WRTC = ON        ;Configuration registers (300000-3000FFh) write-protected
;
;  Boot Block Write Protection bit
;    CONFIG WRTB = OFF        ;Boot Block (000000-0007FFh) not write-protected
;    CONFIG WRTB = ON        ;Boot Block (000000-0007FFh) write-protected
;
;  Data EEPROM Write Protection bit
;    CONFIG WRTD = OFF        ;Data EEPROM not write-protected
;    CONFIG WRTD = ON        ;Data EEPROM write-protected
;
;  Table Read Protection Block 0
;    CONFIG EBTR0 = OFF        ;Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
;    CONFIG EBTR0 = ON        ;Block 0 (000800-001FFFh) protected from table reads executed in other blocks
;
;  Table Read Protection Block 1
;    CONFIG EBTR1 = OFF        ;Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
;    CONFIG EBTR1 = ON        ;Block 1 (002000-003FFFh) protected from table reads executed in other blocks
;
;  Table Read Protection Block 2
;    CONFIG EBTR2 = OFF        ;Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
;    CONFIG EBTR2 = ON        ;Block 2 (004000-005FFFh) protected from table reads executed in other blocks
;
;  Table Read Protection Block 3
;    CONFIG EBTR3 = OFF        ;Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
;    CONFIG EBTR3 = ON        ;Block 3 (006000-007FFFh) protected from table reads executed in other blocks
;
;  Boot Block Table Read Protection bit
;    CONFIG EBTRB = OFF        ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
;    CONFIG EBTRB = ON        ;Boot Block (000000-0007FFh) protected from table reads executed in other blocks
;
;
;/MPASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

---

Here is an example of how to use the #CONFIG block:

Code:

---

' PIC18F45K22 With Internal OSC set to 64 Mhz
' FLASH AN LED CONNECTED TO PORTB.0
 #CONFIG
    CONFIG DEBUG = OFF   
    CONFIG XINST = OFF   
    CONFIG STVREN = OFF   
    CONFIG WDTEN = OFF     
    CONFIG FCMEN = OFF     
    CONFIG FOSC = INTIO67 
    CONFIG PLLCFG = ON       
    CONFIG PRICLKEN = ON     
    CONFIG IESO = OFF      ; Two-Speed Start-up disabled
    CONFIG WDTPS = 128      ; 1:128 prescaller for watchdog
    CONFIG BOREN = OFF      ; Brown-out Reset disabled in hardware and software
    CONFIG BORV = 250      ; VBOR set to 2.5 V nominal
    CONFIG MCLRE = EXTMCLR  ; MCLR pin enabled, RE3 input pin disabled
    CONFIG HFOFST = OFF    ; The system clock is held off until the HF-INTOSC is stable.
    CONFIG PBADEN = OFF    ; PORTB<4:0> pins are configured as digital I/O on Reset
    CONFIG CCP2MX = PORTC1  ; CCP2 input/output is multiplexed with RC1
    CONFIG LVP = OFF        ; Single-Supply ICSP disabled
    CONFIG CP0 = OFF        ; Block 0 (000800-001FFFh) not code-protected
    CONFIG CP1 = OFF        ; Block 1 (002000-003FFFh) not code-protected
    CONFIG CPB = OFF        ; Boot block (000000-0007FFh) not code-protected
    CONFIG CPD = OFF        ; Data eeprom not code-protected
    CONFIG WRT0 = OFF      ; Block 0 (000800-001FFFh) not write-protected
    CONFIG WRT1 = OFF      ; Block 1 (002000-003FFFh) not write-protected
    CONFIG WRT2 = OFF      ; Block 2 (4000h-5FFFh) not write-protected
    CONFIG WRT3 = OFF      ; Block 3 (6000h-7FFFh) not write-protected
    CONFIG WRTB = OFF      ; Boot block (000000-0007FFh) not write-protected
    CONFIG WRTC = OFF      ; Configuration registers (300000-3000FFh) not write-protected
    CONFIG WRTD = OFF      ; Data eeprom not write-protected
    CONFIG EBTR0 = OFF      ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
    CONFIG EBTR1 = OFF      ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
    CONFIG EBTRB = OFF      ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
 #ENDCONFIG

    DEFINE OSC 64          'THE 16MHz IS PLL'ed TO 64 MHz
    OSCCON = %01110000    'Set internal osc to 16 Mhz
    OSCTUNE = %01000000  'Turn PLL ON to multiply osc by 4
   
    ANSELA = 0              'ALL ANALOG TO DIGITAL
    ANSELB = 0 
    ANSELC = 0

---

If you get an error like:
[ERROR] program.pbp fatal (34) : Block overflow for #ENCONFIG
that means that there are too many comments in your configs to "fit". Erase some comments and try compiling again.

Some new features in PBP3 make it possible to do conditional defines, and conditional PIC setup.

(Some content plagiarized from here: http://support.melabs.com/threads/26...wfull=1#post38 ... Thanks Darrel!)

Here's an example of how you can set the configuration bits according to the chip being compiled for.
It uses the Conditional Compile directives (#IF/#ELSE/#ENDIF) along with the #CONFIG blocks.

Only the configs for the selected chip will be used.
And if any other chip besides the 25K20 or 25K22 are selected, it will give an error.

Code:

---

#IF __PROCESSOR__ = "18F25K22"
    #config
        CONFIG  FOSC = HSHP
        CONFIG  WDTEN = OFF
        CONFIG  PWRTEN = ON
        CONFIG  BOREN = OFF
        CONFIG  PBADEN = OFF
        CONFIG  MCLRE = INTMCLR
        CONFIG  LVP = OFF
        CONFIG  DEBUG = OFF
        CONFIG  XINST = OFF
    #endconfig
    ANSELA = 0  ; All Digital
    ANSELB = 0
    ANSELC = 0
#ELSE
    #IF __PROCESSOR__ = "18F25K20"
        #config
            CONFIG  FOSC = HS
            CONFIG  WDTEN = OFF
            CONFIG  PWRT = ON
            CONFIG  BOREN = OFF
            CONFIG  PBADEN = OFF
            CONFIG  MCLRE = OFF
            CONFIG  LVP = OFF
            CONFIG  DEBUG = OFF
            CONFIG  XINST = OFF
        #endconfig
        ANSEL = 0  ; All Digital
        ANSELH = 0
    #ELSE
        #ERROR "This program does not support the " + __PROCESSOR__
    #ENDIF
#ENDIF

---

Note that it also sets the ANSEL? registers differently for each chip. Anything else specific to a particular chip can be set this way too.

Some things to remember:
PBP can not use the XINST ,"Instuction set extension and indexed addressing mode", so make sure it is never turned on.
LVP is another issue. Just leave this off as well.

Some older chips like a slightly different context. Let's take a PIC16F628A for example:
Here are the default configs:

Code:

---

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  The #CONFIG block is passed directly to the asm file, but PBP will replace it
;  automagically with the contents of a user-defined #CONFIG block if one is
;  found in the PBP source program.

#CONFIG
    ifdef PM_USED
        device  pic16F628A, xt_osc, wdt_on, mclr_on, lvp_off, protect_off
    else
        __config _XT_OSC & _WDT_ON & _MCLRE_ON & _LVP_OFF & _CP_OFF
    endif
#ENDCONFIG

---

(The first part of this conditional config statment checks to see if the PM assembler is used. Since code for the newer chips can't be assembled with PM, I always chose MPASM.)
You have to use a format like this for these older chips: __config _x & _y & _z

Melanie,
Can you help me with this?
I cannot get the protection to work. My devices are a 18F2680 and a 18F2620.
Here is my code;
__CONFIG _CONFIG5L, _CP_ALL & _DATA_CP_ON
__CONFIG _CONFIG5H, _CP_ALL & _DATA_CP_ON

As you can see I tried it in bothe high and low registers. This is what I get when I try to compile;
Symbol not previously defined (_CP_ALL)
Symbol not previously defined (_DATA_CP_ON)
Thanks for any help!
Ray

Sorry, I wish I was Melanie, but I have not seen her around lately, or even not so lately.
The 18F2680 needs different syntax for those options. Check out post # 42 of this thread.

Here is the syntax to use for the 18F2680:

Code:

---

;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L          EQU  H'FE'    ; Block 0 (000800-003FFFh) code-protected
_CP0_OFF_5L          EQU  H'FF'    ; Block 0 (000800-003FFFh) not code-protected

_CP1_ON_5L          EQU  H'FD'    ; Block 1 (004000-007FFFh) code-protected
_CP1_OFF_5L          EQU  H'FF'    ; Block 1 (004000-007FFFh) not code-protected

_CP2_ON_5L          EQU  H'FB'    ; Block 2 (008000-00BFFFh) code-protected
_CP2_OFF_5L          EQU  H'FF'    ; Block 2 (008000-00BFFFh) not code-protected

_CP3_ON_5L          EQU  H'F7'    ; Block 3 (00C000-00FFFFh) code-protected
_CP3_OFF_5L          EQU  H'FF'    ; Block 3 (00C000-00FFFFh) not code-protected

;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H          EQU  H'BF'    ; Boot block (000000-0007FFh) code-protected
_CPB_OFF_5H          EQU  H'FF'    ; Boot block (000000-0007FFh) not code-protected

_CPD_ON_5H          EQU  H'7F'    ; Data EEPROM code-protected
_CPD_OFF_5H          EQU  H'FF'    ; Data EEPROM not code-protected

---