Re: Now , This is a bug ...
Just my guess: RMW (read modify write) takes too long to execute before being asked to RMW again, thus the nops make it work.
Re: Now , This is a bug ...
Yes, classic symptoms of read-modify-write.
So, now it's not a bug anymore - just sub optimal coding combined with capacitance on the output, high clock frequency and the hardware implementation of the PIC itself.
If the PIC has a LAT register (which yours do have) then use it instead of the PORT register for things that may suffer from RMW issues.
Code:
LED5 VAR LATA.5
LED4 VAR LATA.4
Re: Now , This is a bug ...
I moved your thread because it is a clear example of RMW and can help others (like me).
Robert
:)
Re: Now , This is a bug ...
Quote:
Originally Posted by
HenrikOlsson
If the PIC has a LAT register (which yours do have) then use it instead of the PORT register for things that may suffer from RMW issues.
Code:
LED5 VAR LATA.5
LED4 VAR LATA.4
See Henrik, that's the part I left out due to lack of confidence, due to being a sub optimal coder :D I was thinking it however. Really my FIRST example where I could see that as the issue, thanks for the validation . . . (Backup?) So now I am reasonably sure I was correct. Thanks.
Re: RMW Read modify write
Thank you guys!
Very clear response...
Re: RMW Read modify write
when using the whole port as a data i/o bus is specifying LAT control possible or required for the port ?
Re: RMW Read modify write
Hi Sheldon,
Yes, it's possible. It's not required but generally recommended (I'd say).
You say i/o but you can't use LAT to read the state of the pins when in input mode. If you read LAT you get the state of the output latch, not the state of the actual pins.
/Henrik.
Re: RMW Read modify write
Code:
glcd_fs var LATD.0 ' Font Select pin High = 6x8 , Low = 8x8
glcd_wr var LATD.1 ' Write control pin ( Active Low)
glcd_rd var LATD.2 ' Read control bit ( Active Low)
glcd_ce var LATD.3 ' Chip enable control bit ( Active Low)
glcd_cd var LATD.4 ' Command (high) and Data (low) toggle bit
glcd_rst var LATD.5 ' Reset control bit (Active Low)
glcd_tris var TRISE ' Data bus direction
glcd_dat var PORTE ' LCD 8 bit data bus
glcd_sta0 var PORTE.0 ' Status Bit 0 - Status Read - Command excute capability - 0 = not avaialble / 1 = Available
glcd_sta1 var PORTE.1 ' Status Bit 1 - Status Read - Data Read/Write capability - 0 = not avaialble / 1 = Available
yes the 8 bits of the port are used as both input / output
i would think PBP uses the LAT registers in the above use ???
i um PBP uses the LAT
Re: RMW Read modify write
Not sure I understand the question, if there is any....
In short:
* To put data on the bus, write to the LATx register
* To read data from the bus, read from PORTx register
If you doYou can do glcd_wr = 1 but you can not do HIGH glcd_wr. HIGH/LOW etc only works on PORTx
/Henrik.
Re: RMW Read modify write
Code:
glcd_dat var PORTE ' LCD 8 bit data bus
as this is 8bit data port with the TRIS set at $00 or $FF
Code:
glcd_tris var TRISE ' Data bus direction
would PBP uses LAT port registers internally ?
Re: RMW Read modify write
assuming you have lat registers on your pic chip , porte is not equal to late they are separate registers . check the memory map of your chip.
pbp has no glcd native functions, whether your "glcd library" uses late is completely dependent on how the library was written .
if you define your "data bus" as porte I would expect it will not use lat regs (that would probably require two defines , one for each direction)
and lastly rmw has no impact at all when you are writing to the whole port
Re: RMW Read modify write