;****************************************************************** ; * ; Filename: 16F1823 LCD Test.asm * ; Author: Mike McLaren, K8LH * ; (C)2010: Micro Application Consultants * ; : All Rights Reserved * ; Date: 29-Nov-11 * ; * ; 16F1823 driving ez-lcd v1 (12F635) LCD interface * ; * ; * ; * ; MPLab: 8.80 (tabs=8) * ; MPAsm: 5.43 * ; * ;****************************************************************** #include errorlevel -302 list st=off ; no symbol table in LST file radix dec __config _CONFIG1, _FOSC_INTOSC & _WDTE_OFF __config _CONFIG2, _PLLEN_OFF & _LVP_OFF ;--< variables >--------------------------------------------------- temp equ 0x20 ; lcd subroutines delayhi equ 0x21 ; DelayCy() subsystem var count equ 0x22 ; ;--< constants >--------------------------------------------------- #define MASK(X) (1<<(X)) brgval equ (16000000/57600/4)-1 ; 57600, BRGH=1, BRG16=1 #define line1 0x80 #define line2 0xC0 ;================================================================== ; K8LH DelayCy() subsystem macro generates four instructions = ;================================================================== radix dec clock equ 16 ; 4, 8, 12, 16, 20 (MHz), etc. usecs equ clock/4 ; cycles/microsecond multiplier msecs equ clock/4*1000 ; cycles/millisecond multiplier DelayCy macro delay ; 11..327690 cycle range movlw high((delay-11)/5)+1 movwf delayhi movlw low ((delay-11)/5) call uDelay-((delay-11)%5) endm ;****************************************************************** ; reset vector * ;****************************************************************** org 0x0000 v_reset goto init ; |B0 ;****************************************************************** ; interrupt vector * ;****************************************************************** org 0x0004 v_int ;****************************************************************** ; main init * ;****************************************************************** init banksel PORTA ; bank 0 |B0 clrf PORTA ; |B0 clrf PORTC ; |B0 banksel ANSELA ; bank 3 |B3 clrf ANSELA ; set digital I/O |B3 clrf ANSELC ; set digital I/O |B3 banksel LATA ; bank 2 |B2 movlw b'00000001' ; |B2 movwf LATA ; set TX pin to 'stop' state |B2 clrf LATC ; |B2 banksel TRISA ; bank 1 |B1 movlw b'00000010' ; RA1/RX input |B1 movwf TRISA ; |B1 clrf TRISC ; |B1 ; ; /* ; * setup INTOSC for 16 MHz ; */ ; osccon = 0b01111010; // setup 16 MHz INTOSC ; while(!oscstat.HFIOFS); // wait for osc stable ; apfcon.RXDTSEL = 1; // put RX on RA1 pin ; apfcon.TXCKSEL = 1; // put TX on RA0 pin ; banksel OSCCON ; bank 1 |B1 movlw b'01111010' ; |B1 movwf OSCCON ; setup 16-MHz INTOSC |B1 stable btfss OSCSTAT,HFIOFS ; osc stable? yes, skip, else |B1 bra stable ; loop (wait until stable) |B1 banksel APFCON ; bank 2 |B2 bsf APFCON,RXDTSEL ; put RX on RA1 pin |B2 bsf APFCON,TXCKSEL ; put TX on RA0 pin |B2 ; /* ; * configure EUSART for 57600 baud operation ; */ ; spbrg = brgval; // ; baudcon.BRG16 = 1; // use 16-bit brg clock ; txsta = 1< D4..D7 = RC0..RC3, RS = RC4, and E = RC5 (but ; delays will have to be put back into the code) ; ;PutNyb ; andlw 0x0F ; RS = 0 |B0 ; skpnc ; |B0 ; iorlw 0x10 ; RS = 1 |B0 ; movwf PORTC ; |B0 ; bsf PORTC,5 ; E = 1 |B0 ; bcf PORTC,5 ; E = 0 |B0 ; return ; |B0 ;****************************************************************** ; K8LH DelayCy() 16-bit uDelay (11..327690 cycle) subroutine * ;****************************************************************** nop ; entry for (delay-11)%5 == 4 |B0 nop ; entry for (delay-11)%5 == 3 |B0 nop ; entry for (delay-11)%5 == 2 |B0 nop ; entry for (delay-11)%5 == 1 |B0 uDelay addlw -1 ; subtract 5 cycle loop time |B0 skpc ; borrow? no, skip, else |B0 decfsz delayhi,F ; done? yes, skip, else |B0 goto uDelay ; do another loop |B0 return ; return with C = Z = 0 |B0 ;****************************************************************** end