'**************************************************************** '* Name : NEW_K40_APA102C_24test.bas * '* Date : 01-23-18 * '* Version : 1.0 * '* Notes : Demo how to use APA102C (DOT-STAR) on * '**************************************************************** ' RE-WRITTEN FOR USE W/18F27K40 E/P @ 64 Mhz. ' ' MODIFIED A/D ROUTINE FOR NEW CHANNEL REGISTER AND CONTROL BITS. ' 'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ' AND NOW ON WITH THE CODE...... 'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX DEFINE OSC 64 DEFINE NO_CLRWDT 1 DEFINE LOADER_USED 1 DEFINE WRITE_INT 1 #CONFIG CONFIG FEXTOSC = OFF ;HS (crystal oscillator) above 8 MHz; PFM set to high power CONFIG RSTOSC = HFINTOSC_64MHZ ;EXTOSC operating per FEXTOSC bits (device manufacturing default) CONFIG CLKOUTEN = OFF ;CLKOUT function is disabled CONFIG CSWEN = ON ;Writing to NOSC and NDIV is allowed CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled CONFIG MCLRE = EXTMCLR ;If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR CONFIG PWRTE = ON ;Power up timer enabled CONFIG LPBOREN = ON ;ULPBOR ENABLED CONFIG BOREN = ON ;Brown-out Reset enabled according to SBOREN CONFIG BORV = VBOR_245 ;Brown-out Reset Voltage (VBOR) set to 2.45V CONFIG ZCD = OFF ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON CONFIG PPS1WAY = OFF ;PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) CONFIG STVREN = ON ;Stack full/underflow will cause Reset CONFIG DEBUG = OFF ;Background debugger disabled CONFIG XINST = OFF ;Extended Instruction Set and Indexed Addressing Mode disabled CONFIG WDTCPS = WDTCPS_31 ;Divider ratio 1:65536; software control of WDTPS CONFIG WDTE = OFF ;WDT DISabled regardless of sleep CONFIG WDTCWS = WDTCWS_7 ;window always open (100%); software control; keyed access not required CONFIG WDTCCS = LFINTOSC ;WDT reference clock is the 31.0 kHz LFINTOSC CONFIG WRT0 = OFF ;Block 0 (000800-003FFFh) not write-protected CONFIG WRT1 = OFF ;Block 1 (004000-007FFFh) not write-protected CONFIG WRT2 = OFF ;Block 2 (008000-00BFFFh) not write-protected CONFIG WRT3 = OFF ;Block 3 (00C000-00FFFFh) not write-protected CONFIG WRT4 = OFF ;Block 4 (010000-013FFFh) not write-protected CONFIG WRT5 = OFF ;Block 5 (014000-017FFFh) not write-protected CONFIG WRT6 = OFF ;Block 6 (018000-01BFFFh) not write-protected CONFIG WRT7 = OFF ;Block 7 (01C000-01FFFFh) not write-protected CONFIG WRTC = OFF ;Configuration registers (300000-30000Bh) not write-protected CONFIG WRTB = OFF ;Boot Block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ;Data EEPROM not write-protected CONFIG SCANE = OFF ;Scanner module is available for use, SCANMD bit can control the module CONFIG LVP = OFF ;HV on MCLR/VPP must be used for programming CONFIG CP = OFF ;UserNVM code protection disabled CONFIG CPD = OFF ;DataNVM code protection disabled CONFIG EBTR0 = OFF ;Block 0 (000800-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ;Block 1 (004000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ;Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ;Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks CONFIG EBTR4 = OFF ;Block 4 (010000-013FFFh) not protected from table reads executed in other blocks CONFIG EBTR5 = OFF ;Block 5 (014000-017FFFh) not protected from table reads executed in other blocks CONFIG EBTR6 = OFF ;Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks CONFIG EBTR7 = OFF ;Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks #ENDCONFIG ' ******************************************************************** ' Declare Port Variables ' ******************************************************************** ANALOG_0 VAR PORTA.0 '1-RED COLOR ADJUSTMENT POT (DEVELOPMENT ONLY) ANALOG_1 VAR PORTA.1 '1-GREEN COLOR ADJUSTMENT POT (DEVELOPMENT ONLY) ANALOG_2 VAR PORTA.2 '1-BLUE COLOR ADJUSTMENT POT (DEVELOPMENT ONLY) ANALOG_3 VAR PORTA.3 '1-LIGHT DEPENDENT RESISTOR INPUT TESTPIN VAR LATA.4 '0-(NU) PORT A.4 OUTPUT ANALOG_4 VAR PORTA.5 '1-ANALOG INPUT CHANNEL 4 (AUDIO INPUT) OSC2 VAR PORTA.6 '0-OUTPUT (SPARE NU) OSC1 VAR PORTA.7 '1-INPUT (SPARE NU) MAXCHANNELS CON 5 ADSCRATCH VAR WORD 'SCRATCH VARIABLE VOLTS VAR WORD[MAXCHANNELS] 'A/D RESULT ARRAY CHANNEL VAR BYTE 'A/D CHANNEL BEING SELECTED COWS_HOME VAR BIT '----------- Initialization ------------------------------- clear LATA = %00000000 'PRESET PORT VALUES BEFORE ENABLING THEM AS OUTPUTS LATB = %11010000 LATC = %11010000 TRISA = %10101111 'INITIALIZE PORT DIRECTIONS TRISB = %10100011 'INITIALIZE PORT DIRECTIONS TRISC = %10000100 'INITIALIZE PORT DIRECTIONS '---------------- PERIPHERAL PIN SELECT MODULE ----------------------- asm ; Unlock sequence BCF INTCON,GIE BANKSEL PPSLOCK MOVLW 055h MOVWF PPSLOCK MOVLW 0aah MOVWF PPSLOCK BCF PPSLOCK,PPSLOCKED BSF INTCON,GIE endasm RX1PPS = $17'%00010111 'UART1 RX INPUT TO PIN RC7 RC6PPS = $09'%00001001 'UART1 TX OUTPUT TO PIN RC6 RX2PPS = $0F'%00001111 'UART2 RX INPUT TO PIN RB7 RB6PPS = $0B'%00001011 'UART2 TX OUTPUT TO PIN RB6 INT0PPS = %00001000 'PORT B.0 INT1PPS = %00001001 'PORT B.1 INT2PPS = %00001010 'PORT B.2 '---------------- PERIPHERAL MODULE DISABLE ----------------------- PMD0 = %01111000 'DISABLE ALL PMD1 = %11111100 'DISABLE ALL BUT TMR1,TMR0 PMD2 = %11011111 'DISABLE ALL BUT A/D PMD3 = %11111111 'DISABLE ALL PMD4 = %00111111 'DISABLE ALL BUT UART1,UART2 PMD5 = %11111111 'DISABLE ALL '---------------- OSCILLATOR & WATCHDOG TIMER ----------------------- OSCCON1 = %00000000 '64 Mhz. INTERNAL Clock OSCCON2 = %00000000 OSCFRQ = %00001000 'SET INTOSC FREQ TO 64 Mhz. OSCTUNE = %00000000 OSCEN = %01000000 'INTOSC EXPLICIDLY ENABLED CLKRCON = %00000000 'DISABLED CLKRCLK = %00000000 'FOSC WDTCON0 = %00000000 '----------------- PORT A CONFIGURATION ------------------------------ ANSELA = %00101111 'PORTS A5,A3,A2,A1,A0 ANALOG WPUA = %00000000 'WEAK PULLUP'S DISABLED ODCONA = %00000000 'SINK & SOURCE SLRCONA = %00000000 'MAXIMUM SLEW RATE INLVLA = %00000000 'TTL LEVELS IOCAN = %00000000 'INTERRUPT ON CHANGE BIT'S DISABLED(NEGATIVE) IOCAP = %00000000 'INTERRUPT ON CHANGE BIT'S DISABLED(POSITIVE) '----------------------- ANALOG CONTROL REGISTERS ----------------------- FVRCON = %00000000 'VOLTAGE REFERENCE DISABLED DAC1CON0 = %00000000 'D/A DISABLED ADCON0 = %10000100 'ADON,SINGLE CONVERSION,RIGHT JUSTTIFIED ADCON2 = %00000000 'BASIC LEGACY MODE ADCLK = %00011111 'FOSC/64 ADREF = %00000000 'AVSS,AVDD ADPCH = %00000000 'A/D CHANNEL NUMBER ADACQ = %00000000 'ACQ TIME NOT INCLUDED ADCAP = %00000000 'NO ADDITIONAL CAPACITANCE ADACT = %00000000 'NO RETRIGGER GOTO Main: '********************************************************************* QUICKREADAD: 'READ SYSTEM A/D VOLTAGES '********************************************************************* CHANNEL = 5 ADCON0 = $84 ' Set A/D to On, RIGHT JUSTIFIED ADPCH = 13 'AUDIO INPUT TO PROCESSOR PAUSEUS 40 ADCON0.0 = 1 ' START CONVERSION NXTQAD: IF ADCON0.0 = 1 THEN NXTQAD 'WAIT FOR A/D TO FINISH VOLTS(CHANNEL) = (((ADRESH & $3) << 8) + ADRESL) 'BUILD SENSOR WORD (RIGHT JUSTIFIED) ADSCRATCH = VOLTS(CHANNEL) IF ADSCRATCH.15 = 1 THEN VOLTS(CHANNEL) = 0 RETURN 'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 'XXXXXXXXXXXXXXXXXXXXXXXXX Main program XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Main: REPEAT GOSUB QUICKREADAD: 'READ SYSTEM A/D VOLTAGES UNTIL COWS_HOME 'I DON'T THINK THEY ARE HOME YET? END STOP