2nd Set of Eyes - with my Config settings for PIC16F1825 - running internal 32mhz OSC

[dw_picbasic]

Hello all,
I've ordered a few PIC16F1825 - and I'm excited about the internal 32Mhz OSC in this chip.
I've been looking at the Datasheet and the PBP3 config file for this device - and I think I understand the config settings in order to turn switch to the internal 32Mhz OSC. If I understand correctly - its running an 8Mhz clock with a 4x PLL to bump it up to 32Mhz

Is anyone running this chip this way - and could you let me know if I have the config settings ok?
Sincere thanks!

#CONFIG
__CONFIG _CONFIG1, _FCMEN_OFF & _IESO_OFF & _FOSC_INTOSC & _PLLEN_ON & _WDTE_SWDTEN & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _PWRTE_OFF
__CONFIG _CONFIG2, _LVP_OFF

#ENDCONFIG

OSCCON = %11110100
'----------------------------------------------------------------------------------------------------------------------
' OSCCON (FOSC and SCS Bits 2-0) set to 100 and FOSC_INTOSC set in #CONFIG above
' OSCCON (IRCF bits 3:0) set to 1110 - this sets the 8Mhz Clock - and the 4X PLL set above in #CONFIG will multiply to 32Mhz
' OSCCON (SPLLEN bit 7) PLL enable-bit enables 4xPLL


DEFINE OSC 32 ' Tells PBP we are running at 32MHz

[richard]

config looks ok while that osccon setting will work

osccon bit 7 SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Word 2 = 1: ie & _PLLEN_ON
SPLLEN bit is ignored. 4xPLL is always enabled (subject to oscillator requirements)

and
osccon bit 2 is Unimplemented: Read as ‘0’

so osccon = $70 ; is the way i do it %01110000

you can also wait till OSCSTAT.6 is set [pll ready]
before any functions are used that need clock stability

while !OSCSTAT.6 : wend ;pll ready

[dw_picbasic]

Thank you Richard!
Much appreciate!


Am I correct about the following also:
16mhz internal clock: Set PLLEN off - and set IRCF = 1111
8mhz internal clock: Set PLLEN off - and set IRCF = 1110

[richard]

Am I correct about the following also:
16mhz internal clock: Set PLLEN off - and set IRCF = 1111
8mhz internal clock: Set PLLEN off - and set IRCF = 1110


the x4pll only works for intosc = 8mhz or suitable ext osc
with no pll intosc from datasheet :-
9004

[dw_picbasic]

Thanks again - Richard!
Much appreciate!