18f27k40 - adc settings

[longpole001]

hI GUYS ,

Wondered if anyone has working ADC code that setup the new k40 chips that would be good for a starting reference

he current code uses ADCIN , but now the structure has changed not sure if it will be the best way for the new K40 chip

There are lot of new registers in The ADC in this chip which i am working though
and would like to make use of the new computational operation , to remove the way i currently do average of ADC readings

Cheers


sheldon

[mpgmike]

; --- *** ADC Related SFRs *** -----------------------------------------------------------------------------------------
ADCON0 = %10010100 ;.7 = 1/0, .0 = GO
ADPCH = %00010101 ;For Keypad, ANC5

ADC VAR WORD

ADCON0.0 = 1
DO
LOOP WHILE ADCON0.0 = 1
ADC.HIGHBYTE = ADRESH
ADC.LOWBYTE = ADRESL

[longpole001]

mike that may work ok , for most i guess , just all the other settings , as clock source, tad rate , internal ref , gain multilpier options on VFR using the count register for samples options , this chip has a lot of stuff in the adc

also note the errata on the adc issues for this chip which may be of interest as well

guess i am still reading and noting stuff in the program , not just for this program but for others that will eventually migrate to the k40 range

just wish microchip had made the k42 with 64/80 pin options , with the more than 128k LOL , just wishing

studdiing what i can on this new chip

[Dave]

Why Yes Sheldon I do. Try this configuration, It is for operation in CLASIC mode.

[longpole001]

thanks dave for the adc registers , also pickup on some other setting that ill show in the config , although they are not changed from POR

i am still working out notes on the release pbp3.1.1 on the 18fxxk40 series


i need hserout2 using usart2 on the PPS default pins , seem the default pins may lock out the ICSP if not changed ??



THIS FILE HAS BEEN UPDATED FOR PBP 3.1.1

The function of the 18FxxK40 devices differs somewhat from other PIC18 parts.
Because of this, the following commands are configured a bit differently when
executed on the 18FxxK40 devices.

--------------------------------------------------------------------------------
HPWM

Use the following PBP DEFINE statements to specify the output pins for HPWM.
Check the Microchip datasheet (Peripheral Pin Select PPS) for the pins allowed
on each CCP/PWM channel. The PPS peripheral will automatically be configured
for the specified output pin upon execution of HPWM. When used on devices other
than the 18FxxK40, these defines will only control the Data Direction SFRs (TRIS).

These defines set PPS SFRs only once at program initialization. You may
change the PWM output pin at any pint in your program code by modifying
the PPS SFRs.


DEFINE CCP1_REG PORTC 'Channel-1 port
DEFINE CCP1_BIT 2 'Channel-1 bit
DEFINE CCP2_REG PORTC 'Channel-2 port
DEFINE CCP2_BIT 1 'Channel-2 bit
DEFINE CCP3_REG PORTC 'Channel-3 port
DEFINE CCP3_BIT 3 'Channel-3 bit
DEFINE CCP4_REG PORTG 'Channel-4 port
DEFINE CCP4_BIT 3 'Channel-4 bit
DEFINE CCP5_REG PORTG 'Channel-5 port
DEFINE CCP5_BIT 4 'Channel-5 bit
DEFINE CCP6_REG PORTE 'Channel-6 port
DEFINE CCP6_BIT 6 'Channel-6 bit
DEFINE CCP7_REG PORTE 'Channel-7 port
DEFINE CCP7_BIT 7 'Channel-7 bit

CCP and PWM peripherals are both supported by HPWM.


DEFAULT CCP PINS SET FOR UNUSED HPWM CHANNELS! If CCP_REG DEFINEs are set
for unused channels, either explicitly or by default, the ports/pins specified
as CCP/PWM outputs may not function as normal I/O until the PPS SRFs are cleared
in your program code. To remove a default setting, define the CCPx_REG as 0,
for example:

DEFINE CCP1_REG PORTC 'Channel-1 port
DEFINE CCP1_BIT 2 'Channel-1 bit
DEFINE CCP2_REG 0 'Channel-2 UNUSED
DEFINE CCP2_BIT 0 'Channel-2 bit
DEFINE CCP3_REG 0 'Channel-3 UNUSED
DEFINE CCP3_BIT 0 'Channel-3 bit
DEFINE CCP4_REG 0 'Channel-4 UNUSED
DEFINE CCP4_BIT 0 'Channel-4 bit

Default output pins if no DEFINE is used:

2xK40 4xK40 6xK40
CCP1 RC2 RC2 RC2
CCP2 RC1 RC1 RC1
CCP3/PWM3 RC6* RD1 RC3
CCP4/PWM4 RA7 RA7 RG3
CCP5 RG4
PWM6 RE6
PWM7 RE7

* Note that default CCP3/PWM3 setting on 28-pin devices conflicts with the default
TX1 setting described below.

--------------------------------------------------------------------------------
HSEROUT/HSEROUT2

Use the following PBP DEFINE statements to specify the output pins for HSEROUT
and HSEROUT2. Check the Microchip datasheet (Peripheral Pin Select PPS) for the
pins allowed on each EUSART. The PPS peripheral will automatically be configured
for the specified RX/TX pins only once after reset or power up. This allows the
PPS SFRs to be changed at runtime to relocate the RX/TX pins as needed. These
defines will have no effect when code is executed on devices other than the
18FxxK40.

DEFINE HSER_RXREG PORTC
DEFINE HSER_RXBIT 7
DEFINE HSER_TXREG PORTC
DEFINE HSER_TXBIT 6
DEFINE HSER2_RXREG PORTB
DEFINE HSER2_RXBIT 5
DEFINE HSER2_TXREG PORTB
DEFINE HSER2_TXBIT 4


Default output pins if no DEFINE is used:

2xK40 4xK40 6xK40
RX1 RC7 RC7 RC7
TX1 RC6* RC6 RC6
RX2 RB5** RB5** RG2
TX2 RB4** RB4** RG1

* Note that default TX1 setting on 28-pin devices conflicts with the default
CCP3/PWM3 setting described above.

** RX2/TX2 defaults changed for some devices in PBP 3.1.1 to avoid ICSP lockout.

--------------------------------------------------------------------------------
I2CREAD/I2CWRITE

The memory map of the 18F4xK40 forces PBP to reduce the I2CREAD/I2CWRITE clock
frequency slightly to allow I2C operation on PORTE pins. If you aren't using
I2CREAD/I2CWRITE on PORTE, you may use the following define to maximize the
clock frequency on ports A, B, C and D.

DEFINE I2C_ONLYABCD 1

This define has no effect on 18F2xK40 and 18F6xK40 devices.

[Dave]

Sheldon, I have never had ICSP lockout issues with the 18F27K40 devices. I rarely use the ICSP option anyways as I always use a boot loader.