Pbp3 - pic18f87k22 / pic18f67k22 setting config typo error ???

[longpole001]

Hi Guys ,

as per normal when i am implementing a new cpu , i refer to the INFO file for its config, then go through the datasheet to see what it setting or not as dephalt

The setting for CONFIG7L in the datasheet shows it is EBTR0 - EBTR7 ( TABLE 28-1 ) spelling
and CONFIG7H in datasheet shows EBTRB spelling

when looking at the INFO file for both 18f67k22 , 18f87k22 it shows "CONFIG EBRT0- EBRT7 = OFF " , "EBRTB = OFF"

When doing a compile the INFO file is correct in what PBP expects it as EBRT0-7 , EBRTB , , but its clearly not the same name spelling as the datasheet it is setting the bits config for

i have not checked if these setting actually protect the read block as yet on the chip

it is now an typo error that PBP now expects and now must use for now or perhaps the datasheet got it wrong ,( i but doubt it)
cheers

Sheldon
8267




;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; File: PIC18F87K22.INFO
; Date: 06/02/15
; Generated by melabs File Manager
;
; PICBASIC PRO(tm) Compiler version: 3.0.8
;
; Copyright 2015 microEngineering Labs, Inc. All Rights Reserved
; The content herein is intended to facilitate embedded development using
; PICBASIC PRO Compiler. Reproduction or utilization for other purposes
; is prohibited without written permission from microEngineering Labs, Inc..
;
; microEngineering Labs, Inc.
; 2845 Ore Mill Road STE 4
; Colorado Springs, CO 80904
; 719-520-5323
; fax: 719-520-1867
; http://melabs.com
; [email protected]
;
; Modifications to this file in the \DEVICE_REFERENCE folder will be
; overwritten when you install future upgrades.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;MPASM CONFIG Directive Options
;
; This section is included for reference only. The options below may be
; used with the MPASM CONFIG directive to specify configuration settings
; in the source program using the #CONFIG/#ENDCONFIG block.
;
; The PBP default configuration for the PIC18F87K22 is:
;
; #CONFIG
; CONFIG RETEN = ON ; Enabled
; CONFIG INTOSCSEL = HIGH ; LF-INTOSC in High-power mode during Sleep
; CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected
; CONFIG XINST = OFF ; Disabled
; CONFIG FOSC = HS1 ; HS oscillator (Medium power, 4 MHz - 16 MHz)
; CONFIG PLLCFG = ON ; Enabled
; CONFIG FCMEN = OFF ; Disabled
; CONFIG IESO = OFF ; Disabled
; CONFIG PWRTEN = OFF ; Disabled
; CONFIG BOREN = SBORDIS ; Enabled in hardware, SBOREN disabled
; CONFIG BORV = 3 ; 1.8V
; CONFIG BORPWR = ZPBORMV ; ZPBORMV instead of BORMV is selected
; CONFIG WDTEN = SWDTDIS ; WDT enabled in hardware; SWDTEN bit disabled
; CONFIG WDTPS = 512 ; 1:512
; CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC
; CONFIG EASHFT = ON ; Address Shifting enabled
; CONFIG ABW = XM20 ; 20-bit address bus
; CONFIG BW = 16 ; 16-bit external bus mode
; CONFIG WAIT = OFF ; Disabled
; CONFIG CCP2MX = PORTC ; RC1
; CONFIG ECCPMX = PORTE ; Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3
; CONFIG MSSPMSK = MSK7 ; 7 Bit address masking mode
; CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled
; CONFIG STVREN = ON ; Enabled
; CONFIG BBSIZ = BB2K ; 2K word Boot Block size
; CONFIG DEBUG = OFF ; Disabled
; CONFIG CP0 = OFF ; Disabled
; CONFIG CP1 = OFF ; Disabled
; CONFIG CP2 = OFF ; Disabled
; CONFIG CP3 = OFF ; Disabled
; CONFIG CP4 = OFF ; Disabled
; CONFIG CP5 = OFF ; Disabled
; CONFIG CP6 = OFF ; Disabled
; CONFIG CP7 = OFF ; Disabled
; CONFIG CPB = OFF ; Disabled
; CONFIG CPD = OFF ; Disabled
; CONFIG WRT0 = OFF ; Disabled
; CONFIG WRT1 = OFF ; Disabled
; CONFIG WRT2 = OFF ; Disabled
; CONFIG WRT3 = OFF ; Disabled
; CONFIG WRT4 = OFF ; Disabled
; CONFIG WRT5 = OFF ; Disabled
; CONFIG WRT6 = OFF ; Disabled
; CONFIG WRT7 = OFF ; Disabled
; CONFIG WRTC = OFF ; Disabled
; CONFIG WRTB = OFF ; Disabled
; CONFIG WRTD = OFF ; Disabled
; CONFIG EBRT0 = OFF ; Disabled
; CONFIG EBRT1 = OFF ; Disabled
; CONFIG EBRT2 = OFF ; Disabled
; CONFIG EBRT3 = OFF ; Disabled
; CONFIG EBRT4 = OFF ; Disabled
; CONFIG EBRT5 = OFF ; Disabled
; CONFIG EBRT6 = OFF ; Disabled
; CONFIG EBRT7 = OFF ; Disabled
; CONFIG EBRTB = OFF ; Disabled
; #ENDCONFIG
;
; Use the available options below to construct your configuration directives.
; Please note that ALL DEFAULT CONFIGURATION SETTINGS WILL BE OVERWRITTEN
; when you include a #CONFIG block in your program.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Available configuration settings for PIC18F87K22:
;
;
; VREG Sleep Enable bit
; CONFIG RETEN = ON ;Enabled
; CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
;
; LF-INTOSC Low-power Enable bit
; CONFIG INTOSCSEL = HIGH ;LF-INTOSC in High-power mode during Sleep
; CONFIG INTOSCSEL = LOW ;LF-INTOSC in Low-power mode during Sleep
;
; SOSC Power Selection and mode Configuration bits
; CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
; CONFIG SOSCSEL = LOW ;Low Power SOSC circuit selected
; CONFIG SOSCSEL = DIG ;Digital (SCLKI) mode
;
; Extended Instruction Set
; CONFIG XINST = ON ;Enabled
; CONFIG XINST = OFF ;Disabled
;
; Oscillator
; CONFIG FOSC = RCIO ;External RC oscillator
; CONFIG FOSC = RC ;External RC oscillator, CLKOUT function on OSC2
; CONFIG FOSC = EC1 ;EC oscillator (Low power, DC - 160 kHz)
; CONFIG FOSC = EC1IO ;EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz)
; CONFIG FOSC = EC2 ;EC oscillator (Medium power, 160 kHz - 16 MHz)
; CONFIG FOSC = EC2IO ;EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 16 MHz)
; CONFIG FOSC = INTIO1 ;Internal RC oscillator, CLKOUT function on OSC2
; CONFIG FOSC = INTIO2 ;Internal RC oscillator
; CONFIG FOSC = EC3 ;EC oscillator (High power, 16 MHz - 64 MHz)
; CONFIG FOSC = EC3IO ;EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz)
; CONFIG FOSC = HS1 ;HS oscillator (Medium power, 4 MHz - 16 MHz)
; CONFIG FOSC = HS2 ;HS oscillator (High power, 16 MHz - 25 MHz)
; CONFIG FOSC = XT ;XT oscillator
; CONFIG FOSC = LP ;LP oscillator
;
; PLL x4 Enable bit
; CONFIG PLLCFG = ON ;Enabled
; CONFIG PLLCFG = OFF ;Disabled
;
; Fail-Safe Clock Monitor
; CONFIG FCMEN = OFF ;Disabled
; CONFIG FCMEN = ON ;Enabled
;
; Internal External Oscillator Switch Over Mode
; CONFIG IESO = OFF ;Disabled
; CONFIG IESO = ON ;Enabled
;
; Power Up Timer
; CONFIG PWRTEN = OFF ;Disabled
; CONFIG PWRTEN = ON ;Enabled
;
; Brown Out Detect
; CONFIG BOREN = SBORDIS ;Enabled in hardware, SBOREN disabled
; CONFIG BOREN = NOSLP ;Enabled while active, disabled in SLEEP, SBOREN disabled
; CONFIG BOREN = ON ;Controlled with SBOREN bit
; CONFIG BOREN = OFF ;Disabled in hardware, SBOREN disabled
;
; Brown-out Reset Voltage bits
; CONFIG BORV = 3 ;1.8V
; CONFIG BORV = 2 ;2.0V
; CONFIG BORV = 1 ;2.7V
; CONFIG BORV = 0 ;3.0V
;
; BORMV Power level
; CONFIG BORPWR = ZPBORMV ;ZPBORMV instead of BORMV is selected
; CONFIG BORPWR = HIGH ;BORMV set to high power level
; CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
; CONFIG BORPWR = LOW ;BORMV set to low power level
;
; Watchdog Timer
; CONFIG WDTEN = SWDTDIS ;WDT enabled in hardware; SWDTEN bit disabled
; CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
; CONFIG WDTEN = NOSLP ;WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled
; CONFIG WDTEN = OFF ;WDT disabled in hardware; SWDTEN bit disabled
;
; Watchdog Postscaler
; CONFIG WDTPS = 1048576 ;1:1048576
; CONFIG WDTPS = 524288 ;1:524288
; CONFIG WDTPS = 262144 ;1:262144
; CONFIG WDTPS = 131072 ;1:131072
; CONFIG WDTPS = 65536 ;1:65536
; CONFIG WDTPS = 32768 ;1:32768
; CONFIG WDTPS = 16384 ;1:16384
; CONFIG WDTPS = 8192 ;1:8192
; CONFIG WDTPS = 4096 ;1:4096
; CONFIG WDTPS = 2048 ;1:2048
; CONFIG WDTPS = 1024 ;1:1024
; CONFIG WDTPS = 512 ;1:512
; CONFIG WDTPS = 256 ;1:256
; CONFIG WDTPS = 128 ;1:128
; CONFIG WDTPS = 64 ;1:64
; CONFIG WDTPS = 32 ;1:32
; CONFIG WDTPS = 16 ;1:16
; CONFIG WDTPS = 8 ;1:8
; CONFIG WDTPS = 4 ;1:4
; CONFIG WDTPS = 2 ;1:2
; CONFIG WDTPS = 1 ;1:1
;
; RTCC Clock Select
; CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
; CONFIG RTCOSC = INTOSCREF ;RTCC uses INTRC
;
; External Address Shift bit
; CONFIG EASHFT = ON ;Address Shifting enabled
; CONFIG EASHFT = OFF ;Address Shifting disabled
;
; Address Bus Width Select bits
; CONFIG ABW = XM20 ;20-bit address bus
; CONFIG ABW = XM16 ;16-bit address bus
; CONFIG ABW = XM12 ;12-bit address bus
; CONFIG ABW = MM ;8-bit address bus
;
; Data Bus Width
; CONFIG BW = 16 ;16-bit external bus mode
; CONFIG BW = 8 ;8-bit external bus mode
;
; External Bus Wait
; CONFIG WAIT = OFF ;Disabled
; CONFIG WAIT = ON ;Enabled
;
; CCP2 Mux
; CONFIG CCP2MX = PORTC ;RC1
; CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
;
; ECCP Mux
; CONFIG ECCPMX = PORTE ;Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3
; CONFIG ECCPMX = PORTH ;Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4
;
; MSSP address masking
; CONFIG MSSPMSK = MSK7 ;7 Bit address masking mode
; CONFIG MSSPMSK = MSK5 ;5 bit address masking mode
;
; Master Clear Enable
; CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
; CONFIG MCLRE = OFF ;MCLR Disabled, RG5 Enabled
;
; Stack Overflow Reset
; CONFIG STVREN = ON ;Enabled
; CONFIG STVREN = OFF ;Disabled
;
; Boot Block Size
; CONFIG BBSIZ = BB2K ;2K word Boot Block size
; CONFIG BBSIZ = BB1K ;1K word Boot Block size
;
; Background Debug
; CONFIG DEBUG = OFF ;Disabled
; CONFIG DEBUG = ON ;Enabled
;
; Code Protect 00800-03FFF
; CONFIG CP0 = OFF ;Disabled
; CONFIG CP0 = ON ;Enabled
;
; Code Protect 04000-07FFF
; CONFIG CP1 = OFF ;Disabled
; CONFIG CP1 = ON ;Enabled
;
; Code Protect 08000-0BFFF
; CONFIG CP2 = OFF ;Disabled
; CONFIG CP2 = ON ;Enabled
;
; Code Protect 0C000-0FFFF
; CONFIG CP3 = OFF ;Disabled
; CONFIG CP3 = ON ;Enabled
;
; Code Protect 10000-13FFF
; CONFIG CP4 = OFF ;Disabled
; CONFIG CP4 = ON ;Enabled
;
; Code Protect 14000-17FFF
; CONFIG CP5 = OFF ;Disabled
; CONFIG CP5 = ON ;Enabled
;
; Code Protect 18000-1BFFF
; CONFIG CP6 = OFF ;Disabled
; CONFIG CP6 = ON ;Enabled
;
; Code Protect 1C000-1FFFF
; CONFIG CP7 = OFF ;Disabled
; CONFIG CP7 = ON ;Enabled
;
; Code Protect Boot
; CONFIG CPB = OFF ;Disabled
; CONFIG CPB = ON ;Enabled
;
; Data EE Read Protect
; CONFIG CPD = OFF ;Disabled
; CONFIG CPD = ON ;Enabled
;
; Table Write Protect 00800-03FFF
; CONFIG WRT0 = OFF ;Disabled
; CONFIG WRT0 = ON ;Enabled
;
; Table Write Protect 04000-07FFF
; CONFIG WRT1 = OFF ;Disabled
; CONFIG WRT1 = ON ;Enabled
;
; Table Write Protect 08000-0BFFF
; CONFIG WRT2 = OFF ;Disabled
; CONFIG WRT2 = ON ;Enabled
;
; Table Write Protect 0C000-0FFFF
; CONFIG WRT3 = OFF ;Disabled
; CONFIG WRT3 = ON ;Enabled
;
; Table Write Protect 10000-13FFF
; CONFIG WRT4 = OFF ;Disabled
; CONFIG WRT4 = ON ;Enabled
;
; Table Write Protect 14000-17FFF
; CONFIG WRT5 = OFF ;Disabled
; CONFIG WRT5 = ON ;Enabled
;
; Table Write Protect 18000-1BFFF
; CONFIG WRT6 = OFF ;Disabled
; CONFIG WRT6 = ON ;Enabled
;
; Table Write Protect 1C000-1FFFF
; CONFIG WRT7 = OFF ;Disabled
; CONFIG WRT7 = ON ;Enabled
;
; Config. Write Protect
; CONFIG WRTC = OFF ;Disabled
; CONFIG WRTC = ON ;Enabled
;
; Table Write Protect Boot
; CONFIG WRTB = OFF ;Disabled
; CONFIG WRTB = ON ;Enabled
;
; Data EE Write Protect
; CONFIG WRTD = OFF ;Disabled
; CONFIG WRTD = ON ;Enabled
;
; Table Read Protect 00800-03FFF
; CONFIG EBRT0 = OFF ;Disabled
; CONFIG EBRT0 = ON ;Enabled
;
; Table Read Protect 04000-07FFF
; CONFIG EBRT1 = OFF ;Disabled
; CONFIG EBRT1 = ON ;Enabled
;
; Table Read Protect 08000-0BFFF
; CONFIG EBRT2 = OFF ;Disabled
; CONFIG EBRT2 = ON ;Enabled
;
; Table Read Protect 0C000-0FFFF
; CONFIG EBRT3 = OFF ;Disabled
; CONFIG EBRT3 = ON ;Enabled
;
; Table Read Protect 10000-13FFF
; CONFIG EBRT4 = OFF ;Disabled
; CONFIG EBRT4 = ON ;Enabled
;
; Table Read Protect 14000-17FFF
; CONFIG EBRT5 = OFF ;Disabled
; CONFIG EBRT5 = ON ;Enabled
;
; Table Read Protect 18000-1BFFF
; CONFIG EBRT6 = OFF ;Disabled
; CONFIG EBRT6 = ON ;Enabled
;
; Table Read Protect 1C000-1FFFF
; CONFIG EBRT7 = OFF ;Disabled
; CONFIG EBRT7 = ON ;Enabled
;
; Table Read Protect Boot
; CONFIG EBRTB = OFF ;Disabled
; CONFIG EBRTB = ON ;Enabled
;
;
;/MPASM

[HenrikOlsson]

If you look at the MPASM .inc file (ie p18f87k22.inc) where all these settings are defined you'll find that it is called EBRT so the .INFO file matches what the assembler expects. I don't know which is "correct", the datasheet or the .inc file.

/Henrik.

[longpole001]

looking at other info files / other configs i have for 18F chips which use the datasheet ref of EBTR1 -4 ( 18f46k80 )

it seems PBP has done it only for the 18f67k22, 18f87k22 chips , which seems like its typo that PBP has just incorporated for these chips in the compile

[HenrikOlsson]

If anything it's a typo in the MPASM .inc file for the device and PBP needs to follow that in order for it to work.

[longpole001]

yes , just the way its is for these 2 chips , its seems to get the right data in the hex for the programmer config

[pascalou95]

bonjour,
Je voudrais programmer les fusibles du PIC18F2550 correctement pour un bon fonctionnement du programme de ce multi chargeur d'accus.
je ne sais pas comment procéder en picbasic pour écrire les lignes de commande.
Quartz de 4 mhz
pwrt off
mclr off
cdp off
wrt off
je peux fournir le programme complet de ce chargeur en picbasic.

****
'* Nom : CBAT2550.PBP *
'* Auteur : Pascal *
'* Date : septembre 2017 *
'* Version: 1.0 config 18F2550_CBAT.INC *
'************************************************* ***************


DATA @0,1,1,5,5,5,5,5,5,0,0,100,100,0,0,90,90,1,1,94,94 ,0,0,1,1


DEFINE LCD_DREG PORTB ' PORTB I/O du LCD
DEFINE LCD_DBIT 4 ' Bit d'inisialisation
DEFINE LCD_RSREG PORTB
DEFINE LCD_RSBIT 0 ' Bit RS sur RB0
DEFINE LCD_EREG PORTB
DEFINE LCD_EBIT 1 ' Bit E sur RB1
DEFINE LCD_BITS 4 ' 4 bits de données
DEFINE LCD_LINES 2 ' LCD 2 lignes
DEFINE LCD_COMMANDS 500 ' Délais de la commande
DEFINE LCD_DATAUS 50 ' Délais des données


DEFINE ADC_BITS 10 ' Résolution de l'ADC à 10 bits
DEFINE ADC_CLOCK 3 ' Réglage de l'horloge de l'ADC (OSC/32= 2, rc = 3)
DEFINE ADC_SAMPLEUS 500 ' Vitesse de conversion


DEFINE OSC 48 ' Horloge du PIC à 48MHz


DEFINE BUTTON_PAUSE 100

[richard]

google translate

hello, I would like to program the fuses of the PIC18F2550 correctly for a good operation of the program of this multi battery charger. I do not know how to proceed in picbasic to write the command lines. Quartz of 4 mhz pwrt off mclr off cdp off wrt off I can supply the full program of this charger in picbasic ..

you don't say what version of pbp you are using
for pbp3 to get an OSC of 48mHz from a 4mHz xtal you would use



#CONFIG
CONFIG PLLDIV = 1
CONFIG CPUDIV = OSC1_PLL2
CONFIG USBDIV = 2
CONFIG FOSC = HSPLL_HS
CONFIG FCMEN = OFF
CONFIG IESO = OFF
CONFIG PWRT = OFF
CONFIG BOR = ON
CONFIG BORV = 3
CONFIG VREGEN = ON
CONFIG WDT = ON
CONFIG WDTPS = 512
CONFIG CCP2MX = ON
CONFIG PBADEN = OFF
CONFIG LPT1OSC = OFF
CONFIG MCLRE = OFF
CONFIG STVREN = ON
CONFIG LVP = OFF
CONFIG XINST = OFF
CONFIG DEBUG = OFF
CONFIG CP0 = OFF
CONFIG CP1 = OFF
CONFIG CP2 = OFF
CONFIG CP3 = OFF
CONFIG CPB = OFF
CONFIG CPD = OFF
CONFIG WRT0 = OFF
CONFIG WRT1 = OFF
CONFIG WRT2 = OFF
CONFIG WRT3 = OFF
CONFIG WRTC = OFF
CONFIG WRTB = OFF
CONFIG WRTD = OFF
CONFIG EBTR0 = OFF
CONFIG EBTR1 = OFF
CONFIG EBTR2 = OFF
CONFIG EBTR3 = OFF
CONFIG EBTRB = OFF
#ENDCONFIG

[pascalou95]

bonjour,
j'utilise la version PBP 4.0.0.0 et MPLAB 8.92.
le quartz est un 4mhz.
je voudrais savoir si je peux et comment programmer les bits fusibles dans pbp et savoir comment cela s’écrit.
je peux vous envoyez, si vous voulez le programme de mon montage, si cela vous permet de mieux comprendre.
pascal

[richard]

Hello,
I use the version PBP 4.0.0.0 and MPLAB 8.92.
the quartz is a 4mhz.

I can send you, if you want the program of my editing, if this allows you to better understand.
pascal



version 4.0.0.0 is the microcode studio version
pbp version is v3.x.x.x or 2.xx


I would like to know if I can and how to program the fuse bits in pbp and know how this is written.

my previous reply is one way that will do it for pbp 3.xxx

its done differently for pbp 2.xxx . I have not used that old version for several years and can offer no help for it
meconfig suggests this


ASM
__config _CONFIG1L, _PLLDIV_1_1L & _CPUDIV_OSC1_PLL2_1L & _USBDIV_2_1L
__config _CONFIG1H, _FOSC_HSPLL_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
__config _CONFIG2L, _PWRT_OFF_2L & _BOR_ON_2L & _BORV_3_2L & _VREGEN_ON_2L
__config _CONFIG2H, _WDT_ON_2H & _WDTPS_512_2H
__config _CONFIG3H, _CCP2MX_ON_3H & _PBADEN_OFF_3H & _LPT1OSC_OFF_3H & _MCLRE_OFF_3H
__config _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
__config _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L
__config _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
__config _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L
__config _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
__config _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L
__config _CONFIG7H, _EBTRB_OFF_7H
ENDASM