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LakisFM1
- 30th May 2014, 17:54
This is simple Led-blink code that does not work.

LED5 flashes normally, and LED 4 stable HIGH.................

Using a 12F1822 (RA4 is not open collector in this PIC).





ASM
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_ON & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_ON & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _PLLEN_ON & _STVREN_OFF & _BORV_HI & _LVP_OFF
ENDASM

DEFINE OSC 32
LED5 VAR PORTA.5
LED4 VAR PORTA.4

OSCCON = %01110000
ANSELA = %00000011 ' AN0 = ANALOG PIN , C1IN0- = ANALOG PIN
TRISA = %00000000

LOOPA:

LED4 = 1
LED5 = 1
PAUSE 100

LED4 = 0
LED5 = 0
PAUSE 100

GOTO LOOPA



when LOOPA modified as above works fine and both LEDs blinking.



LOOPA:

LED4 = 1
LED5 = 1
PAUSE 100

LED4 = 0
PAUSEUS 2 <---
LED5 = 0
PAUSE 100

GOTO LOOPA


EDIT : instead of the 2us pause , i tried another command like modifying a variable , XX = 1 and still works.
So the conclusion is , two LEDx = 0 commands in the row cannot be processed normally (although LEDx = 1 works) .
The UFO's coming ...
Cheers!

Archangel
- 30th May 2014, 19:52
Just my guess: RMW (read modify write) takes too long to execute before being asked to RMW again, thus the nops make it work.

HenrikOlsson
- 30th May 2014, 20:43
Yes, classic symptoms of read-modify-write.
So, now it's not a bug anymore - just sub optimal coding combined with capacitance on the output, high clock frequency and the hardware implementation of the PIC itself.

If the PIC has a LAT register (which yours do have) then use it instead of the PORT register for things that may suffer from RMW issues.

LED5 VAR LATA.5
LED4 VAR LATA.4

Demon
- 31st May 2014, 01:28
I moved your thread because it is a clear example of RMW and can help others (like me).

Robert
:)

Archangel
- 31st May 2014, 04:53
If the PIC has a LAT register (which yours do have) then use it instead of the PORT register for things that may suffer from RMW issues.

LED5 VAR LATA.5
LED4 VAR LATA.4
See Henrik, that's the part I left out due to lack of confidence, due to being a sub optimal coder :D I was thinking it however. Really my FIRST example where I could see that as the issue, thanks for the validation . . . (Backup?) So now I am reasonably sure I was correct. Thanks.

LakisFM1
- 9th June 2014, 13:29
Thank you guys!

Very clear response...

longpole001
- 24th June 2014, 08:18
when using the whole port as a data i/o bus is specifying LAT control possible or required for the port ?

HenrikOlsson
- 24th June 2014, 09:17
Hi Sheldon,
Yes, it's possible. It's not required but generally recommended (I'd say).
You say i/o but you can't use LAT to read the state of the pins when in input mode. If you read LAT you get the state of the output latch, not the state of the actual pins.

/Henrik.

longpole001
- 25th June 2014, 09:41
glcd_fs var LATD.0 ' Font Select pin High = 6x8 , Low = 8x8
glcd_wr var LATD.1 ' Write control pin ( Active Low)
glcd_rd var LATD.2 ' Read control bit ( Active Low)
glcd_ce var LATD.3 ' Chip enable control bit ( Active Low)
glcd_cd var LATD.4 ' Command (high) and Data (low) toggle bit
glcd_rst var LATD.5 ' Reset control bit (Active Low)


glcd_tris var TRISE ' Data bus direction
glcd_dat var PORTE ' LCD 8 bit data bus
glcd_sta0 var PORTE.0 ' Status Bit 0 - Status Read - Command excute capability - 0 = not avaialble / 1 = Available
glcd_sta1 var PORTE.1 ' Status Bit 1 - Status Read - Data Read/Write capability - 0 = not avaialble / 1 = Available




yes the 8 bits of the port are used as both input / output

i would think PBP uses the LAT registers in the above use ???




i um PBP uses the LAT

HenrikOlsson
- 25th June 2014, 09:52
Not sure I understand the question, if there is any....

In short:
* To put data on the bus, write to the LATx register
* To read data from the bus, read from PORTx register

If you do

glcd_wr var LATD.1
You can do glcd_wr = 1 but you can not do HIGH glcd_wr. HIGH/LOW etc only works on PORTx

/Henrik.

longpole001
- 3rd July 2014, 10:52
glcd_dat var PORTE ' LCD 8 bit data bus


as this is 8bit data port with the TRIS set at $00 or $FF



glcd_tris var TRISE ' Data bus direction

would PBP uses LAT port registers internally ?

richard
- 3rd July 2014, 11:22
assuming you have lat registers on your pic chip , porte is not equal to late they are separate registers . check the memory map of your chip.
pbp has no glcd native functions, whether your "glcd library" uses late is completely dependent on how the library was written .
if you define your "data bus" as porte I would expect it will not use lat regs (that would probably require two defines , one for each direction)
and lastly rmw has no impact at all when you are writing to the whole port

longpole001
- 5th July 2014, 05:48
thanks richard