ChrisKiwi
- 21st September 2010, 08:05
Hi all,
Has anybody had this working ? I have the low pin count development board and have had no luck so far. The hardware is working OK, as I have had a pre compiled example from the development kit working. When I try to connect with the CDC example from the PBP USB18 folder I get the
I'm assuming that you still need to add the necessary con-fig fuses ? I have used:
; config1L : No CPU clock divide : USB clock = divide by 2, use 12 MHz xtal = 6MHz = Lo Speed USB
__CONFIG _CONFIG1L, _CPUDIV_NOCLKDIV_1L & _USBDIV_ON_1L
; config1H : Int RC CLK out on OSC2 : PLL under Software control : Primary CLK ENABLED : Failsafe CLK monitor DISABLED : OSC switch over DISABLED
__CONFIG _CONFIG1H, _FOSC_HS_1H & _PLLEN_OFF_1H & _PCLKEN_OFF_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
; config2L : PWRT DISABLED : Brown-Out Reset DISABLED :
__CONFIG _CONFIG2L, _PWRTEN_OFF_2L & _BOREN_OFF_2L
; config2H : WDT Disabled :
__CONFIG _CONFIG2H, _WDTEN_OFF_2H ; & _WDTPS_512_2H
; config3H : MCLR Disabled : Int OSC starts clocking CPU from power up
__CONFIG _CONFIG3H, _MCLRE_OFF_3H & _HFOFST_ON_3H
; config4L : Stack full/underflow will cause Reset : LVP off : 512W boot block size : Disabled (Legacy mode)
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _BBSIZ_OFF_4L & _XINST_OFF_4L
; config5L : Block 0 not code-protected : Block 1 not code-protected
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
; config 5H : Boot block not code-protected : Data EEPROM not write-protected
__CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
; config 6L : Block 0 not write-protected : Block 1 not write-protected
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
; config 6H : Boot block not write-protected : Configuration registers not write-protected : Data EEPROM not write-protected
__CONFIG _CONFIG6H, _WRTB_OFF_6H & _WRTC_ON_6H & _WRTD_OFF_6H
; config 7L : Block 0 not protected from table reads executed in other blocks : Block 1 not protected from table reads executed in other blocks
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
; config 7H : Boot block not protected from table reads executed in other blocks
__CONFIG _CONFIG7H, _EBTRB_OFF_7H
as I was intending to run run low speed. Not using these fuse settings results in compile warnings.
I have read the thread:
http://www.picbasic.co.uk/forum/showthread.php?t=5806&page=2 and in particular Darrel's post as I am using PBP 2.6.
Any feed back or pointers appreciated.
Cheers
Chris
Has anybody had this working ? I have the low pin count development board and have had no luck so far. The hardware is working OK, as I have had a pre compiled example from the development kit working. When I try to connect with the CDC example from the PBP USB18 folder I get the
I'm assuming that you still need to add the necessary con-fig fuses ? I have used:
; config1L : No CPU clock divide : USB clock = divide by 2, use 12 MHz xtal = 6MHz = Lo Speed USB
__CONFIG _CONFIG1L, _CPUDIV_NOCLKDIV_1L & _USBDIV_ON_1L
; config1H : Int RC CLK out on OSC2 : PLL under Software control : Primary CLK ENABLED : Failsafe CLK monitor DISABLED : OSC switch over DISABLED
__CONFIG _CONFIG1H, _FOSC_HS_1H & _PLLEN_OFF_1H & _PCLKEN_OFF_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
; config2L : PWRT DISABLED : Brown-Out Reset DISABLED :
__CONFIG _CONFIG2L, _PWRTEN_OFF_2L & _BOREN_OFF_2L
; config2H : WDT Disabled :
__CONFIG _CONFIG2H, _WDTEN_OFF_2H ; & _WDTPS_512_2H
; config3H : MCLR Disabled : Int OSC starts clocking CPU from power up
__CONFIG _CONFIG3H, _MCLRE_OFF_3H & _HFOFST_ON_3H
; config4L : Stack full/underflow will cause Reset : LVP off : 512W boot block size : Disabled (Legacy mode)
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _BBSIZ_OFF_4L & _XINST_OFF_4L
; config5L : Block 0 not code-protected : Block 1 not code-protected
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
; config 5H : Boot block not code-protected : Data EEPROM not write-protected
__CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
; config 6L : Block 0 not write-protected : Block 1 not write-protected
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
; config 6H : Boot block not write-protected : Configuration registers not write-protected : Data EEPROM not write-protected
__CONFIG _CONFIG6H, _WRTB_OFF_6H & _WRTC_ON_6H & _WRTD_OFF_6H
; config 7L : Block 0 not protected from table reads executed in other blocks : Block 1 not protected from table reads executed in other blocks
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
; config 7H : Boot block not protected from table reads executed in other blocks
__CONFIG _CONFIG7H, _EBTRB_OFF_7H
as I was intending to run run low speed. Not using these fuse settings results in compile warnings.
I have read the thread:
http://www.picbasic.co.uk/forum/showthread.php?t=5806&page=2 and in particular Darrel's post as I am using PBP 2.6.
Any feed back or pointers appreciated.
Cheers
Chris